
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
9397 750 08865
34 of 84
Rev. 02 — 8 October 2001
Product data
PNX8510/11
Philips Semiconductors
Analog Companion Chip
Registers 0x1C through 0x25 must be initialized to zero.
1
R/W
-
MSMS2
Monitor sense status DAC2
0 = Comparator is inactive.
1 = Comparator is active.
0
R/W
-
MSMS1
Monitor sense status DAC1
0 = Comparator is inactive.
1 = Comparator is active.
Bits
Read/
Write
Reset
Value
Name
(Field or Function)
Description
Bits
Read/
Write
Reset
Value
Name
(Field or Function)
Description
Offset 0x26
WSS1
7:0
R/W
-
WSSD[7:0]
Wide screen signalling data
bits 3:0 = Aspect ratio encoding
bits 7:4 = Enhanced services
Offset 0x27
WSS2
7
R/W
0
WSSON
Wide screen signalling enable
0 = wss switched off
1 = wss switched on
6-
Unused
5:0
R/W
-
WSSD[13:8]
Wide screen signalling data
bits 13:11 = Reserved
bits 10:8 = Subtitles
Offset 0x28
RTC1/BCTL1
7
R/W
0
DECFIS
Field sequence detection via RTC
0 = Field sequence as FISE in address 61
1 = Field sequence detection via RTC interface
6
R/W
0
DECCOL
Color detection via RTC interface
0 = Color detection via RTC disabled
1 = Color detection via RTC enabled
Note: The RTCE bit must be set to 1 to enable this feature.
5:0
R/W
0x21
BS
Starting point of color burst in clk cycles
PAL=0x21
NTSC=0x25
Offset 0x29
BCTL2
7:6
-
Unused
5:0
R/W
0x1d
BE
Color burst end point in clk cycles
PAL = 0x1D
NTSC = 0x1D
Offset 0x2A
CGD1
7:0
R/W
-
CG
Copy guard information bits 7:0
Note: The 14 LSBs of the byte carry the information encoded after
the run-in. The 6 MSBs have to carry the CRCC bits in accordance
with the definition of the CGMS encoding format.
Offset 0x2B
CGD2
7:0
R/W
-
CG
Copy guard information bits 15:8
Note: The 14 LSBs of the byte carry the information encoded after
the run-in. The 6 MSBs have to carry the CRCC bits in accordance
with the definition of the CGMS encoding format.
Offset 0x2C
CGD
7
R/W
0
CGEN
Copy guard enable
0 = Disabled
1 = Enabled