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參數(shù)資料
| 型號： | A40MX04-VQG80A |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 6000 GATES, PQFP80 |
| 封裝： | PLASTIC, VQFP-80 |
| 文件頁數(shù)： | 10/78頁 |
| 文件大小： | 515K |
| 代理商： | A40MX04-VQG80A |
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40MX and 42MX Automotive FPGA Families
1- 14
v3.0
CEQ Values for Actel MX FPGAs
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. The equation below shows a
piece-wise linear summation over all components.
Power = VCCA
2 * [(m x C
EQM * fm)Modules +
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2
EQ 1-2
where:
Fixed Capacitance Values
for MX FPGAs (pF)
Determining Average Switching
Frequency
To determine the switching frequency for a design, the
data input values to the circuit must be clearly
understood. The following guidelines represent worst-
case scenarios; these can be used to generally predict the
upper limits of power dissipation.
Modules (CEQM)
3.5
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)
1.4
m
=
Number of logic modules switching at frequency fm
n
=
Number of input buffers switching at frequency fn
p
=
Number of output buffers switching at frequency fp
q1
=
Number of clock loads on the first routed array
clock
q2
=
Number of clock loads on the second routed array
clock
r1
=
Fixed capacitance due to first routed array clock
r2
=
Fixed capacitance due to second routed array clock
CEQM
=
Equivalent capacitance of logic modules in pF
CEQI
=
Equivalent capacitance of input buffers in pF
CEQO
=
Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CL
=
Output load capacitance in p
fm
=
Average logic module switching rate in MHz
fn
=
Average input buffer switching rate in MHz
fp
=
Average output buffer switching rate in MHz
fq1
=
Average first routed array clock rate in MHz
fq2
=
Average second routed array clock rate in MHz
Device Type
r1
routed_Clk1
r2
routed_Clk2
A40MX02
41.4
N/A
A40MX04
68.6
N/A
A42MX09
118
A42MX16
165
A42MX24
185
A42MX36
220
Logic Modules (m)
=
80% of
Combinatorial
Modules
Inputs Switching (n)
=
# of Inputs/4
Outputs Switching (p)
=
# of Outputs/4
First Routed Array Clock Loads (q1)
=
40% of Sequential
Modules
Second Routed Array Clock Loads
(q2)
=
40% of Sequential
Modules
Load Capacitance (CL)
=
35 pF
Average Logic Module Switching
Rate (fm)
=F/10
Average Input Switching Rate (fn)=
F/5
Average Output Switching Rate (fp)=
F/10
Average First Routed Array Clock
Rate (fq1)
=F
Average Second Routed Array Clock
Rate (fq2)
=F/2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX04-VQG80I | 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-VQG80M | 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 80VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 80VQFP |
| A40MX09-PL84 | 制造商:Microsemi SOC Products Group 功能描述: |
| A40P24 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 White, fits 40x24, Steel |
| A-40P24 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 37.00x21.00 fits 40.00x2 |
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