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參數資料
| 型號： | A40MX04-VQG80A |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 6000 GATES, PQFP80 |
| 封裝： | PLASTIC, VQFP-80 |
| 文件頁數： | 2/78頁 |
| 文件大小： | 515K |
| 代理商： | A40MX04-VQG80A |
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40MX and 42MX Automotive FPGA Families
1- 6
v3.0
Power Supply
Automotive MX devices are designed to operate in 5.0V environments. Table 1-1 describes the voltage settings of
automotive MX devices.
Power-Up/Down
When powering up MX devices, VCCA must be greater
than or equal to VCCI throughout the power-up
sequence. If VCCI exceeds VCCA during power-up, either
the input protection junction on the I/Os will be forward-
biased or the I/Os will be at logical High, and ICC rises to
high levels. During power-down, VCCA must be smaller
than or equal to VCCI.
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-
in access to every node in a design, via the use of Silicon
Explorer II. Silicon Explorer II is an integrated hardware
and software solution that, in conjunction with the
Designer software, allow users to examine any of the
internal nodes of the device while it is operating in a
prototyping or a production system. The user can probe
an MX device without changing the placement and
routing of the design and without using any additional
resources. Silicon Explorer II's noninvasive method does
not alter timing or loading effects, thus shortening the
debug cycle and providing a true representation of the
device under actual functional situations.
Silicon
Explorer
II
samples
data
at
100
MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard serial port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification
process
at
their
desks
and
reduces
verification time from several hours per cycle to a few
seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI
and SDO pins in MX devices to select the desired nets for
debugging. The user simply assigns the selected internal
nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is
activated when the MODE pin is held HIGH.
Figure 1-11 on page 1-7 illustrates the interconnection
between Silicon Explorer II and 40MX devices, while
Figure 1-12 on page 1-7 illustrates the interconnection
between Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must
not be programmed. (Refer to "User Security" section on
page 1-5 for the security fuses of 40MX and 42MX
devices). Table 1-2 on page 1-7 summarizes the possible
device configurations for probing.
PRA and PRB pins are dual-purpose pins. When the
"Reserve
Probe
Pin"
is
checked
in
the
Designer software, PRA and PRB pins are reserved as
dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and
"Reserve Probe Pin" is checked, the layout tool will
override the option and place user I/Os on PRA and PRB
pins.
Table 1-1 Voltage Support of Automotive-Grade MX Devices
Device
VCC
VCCA
VCCI
Maximum Input Tolerance
Nominal Output Voltage
40MX
5.0V
–
5.25V
5.0V
42MX
–
5.0V
5.25V
5.0V
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相關代理商/技術參數 |
參數描述 |
|---|---|
| A40MX04-VQG80I | 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數:- 邏輯元件/單元數:- RAM 位總計:36864 輸入/輸出數:157 門數:250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17） |
| A40MX04-VQG80M | 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 80VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 80VQFP |
| A40MX09-PL84 | 制造商:Microsemi SOC Products Group 功能描述: |
| A40P24 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 White, fits 40x24, Steel |
| A-40P24 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 37.00x21.00 fits 40.00x2 |
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