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參數資料
型號: A40MX04-VQG80A
元件分類: FPGA
英文描述: FPGA, 6000 GATES, PQFP80
封裝: PLASTIC, VQFP-80
文件頁數: 43/78頁
文件大小: 515K
代理商: A40MX04-VQG80A
40MX and 42MX Automotive FPGA Families
1- 44
v3.0
tGHL
G-to-Pad LOW
5.0
ns
tLSU
I/O Latch Set-Up
0.8
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad), 32 I/O
9.5
ns
tACO
Array Clock-to-Out (Pad-to-Pad), 32 I/O
13.0
ns
dTLH
Capacity Loading, LOW to HIGH
0.11
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.11
ns/pF
Table 1-14 A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C (Continued)
Parameter
Description
Std. Speed
Units
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
PDF描述
A42MX36-1BG272B FPGA, 2438 CLBS, 36000 GATES, PBGA272
A42MX36-1BGG272B FPGA, 2438 CLBS, 36000 GATES, PBGA272
A42MX36-1PQ208B FPGA, 2438 CLBS, 36000 GATES, PQFP208
A42MX36-1PQ240B FPGA, 2438 CLBS, 36000 GATES, PQFP240
A42MX36-1PQG208B FPGA, 2438 CLBS, 36000 GATES, PQFP208
相關代理商/技術參數
參數描述
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