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參數(shù)資料
| 型號(hào)： | AD7730LBR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 14/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730LBR |
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AD7730/AD7730L
–14–
REV. A
Bit
Location
Bit
Mnemonic
Description
CR3
CR2–CR0
ZERO
RS2–RS0
A zero
must
be written to this bit to ensure correct operation of the AD7730.
Register Selection Bits. RS2 is the MSB of the three selection bits. T he three bits select
which register type the next read or write operation operates upon as shown in T able VIII.
T able VIII. Register Selection
RS2
0
0
0
0
0
1
1
1
1
RS1
0
0
0
1
1
0
0
1
1
RS0
0
0
1
0
1
0
1
0
1
Register
Communications Register (Write Operation)
Status Register (Read Operation)
Data Register
Mode Register
Filter Register
DAC Register
Offset Register
Gain Register
T est Register
Status Register (RS2–RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex
T he Status Register is an 8-bit read-only register. T o access the Status Register, the user must write to the Communications Register
selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. T able IX outlines the bit desig-
nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7
denotes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7730. T he number
in brackets indicates the power-on/reset default status of that bit.
T able IX . Status Register
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY
(1)
STDY
(1)
ST BY (0)
NOREF (0)
MS3 (X )
MS2 (X )
MS1 (X )
MS0 (X )
Bit
Location
Bit
Mnemonic
Description
SR7
RDY
Ready Bit. T his bit provides the status of the
RDY
flag from the part. T he status and function of
this bit is the same as the
RDY
output pin. A number of events set the
RDY
bit high as indi-
cated in T able X VIII.
Steady Bit. T his bit is updated when the filter writes a result to the Data Register. If the filter is
in
FAST
Step
mode (see Filter Register section) and responding to a step input, the
STDY
bit
remains high as the initial conversion results become available. T he
RDY
output and bit are set
low on these initial conversions to indicate that a result is available. If the
STDY
is high, however,
it indicates that the result being provided is not from a fully settled second-stage FIR filter. When the
FIR filter has fully settled, the
STDY
bit will go low coincident with
RDY
. If the part is never placed
into its
FAST
Step
mode, the
STDY
bit will go low at the first Data Register read and it is
not cleared by subsequent Data Register reads.
A number of events set the
STDY
bit high as indicated in T able X VIII.
STDY
is set high along
with
RDY
by all events in the table except a Data Register read.
Standby Bit. T his bit indicates whether the AD7730 is in its Standby Mode or normal mode of
operation. T he part can be placed in its standby mode using the
STANDBY
input pin or by
writing 011 to the MD2 to MD0 bits of the Mode Register. T he power-on/reset status of this bit
is 0 assuming the
STANDBY
pin is high.
No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.3 V, or
either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on comple-
tion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on completion
of a calibration, updating of the calibration registers is inhibited.
T hese bits are for factory use. T he power-on/reset status of these bits vary, depending on the
factory-assigned number.
SR6
STDY
SR5
ST BY
SR4
NOREF
SR3–SR0
MS3–MS0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7730LBR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 600sps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.6KSPS 24BIT SERL 24SOIC W - Tape and Reel |
| AD7730LBR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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