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參數資料
| 型號： | AD7730LBR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 34/52頁 |
| 文件大?。?/td> | 497K |
| 代理商： | AD7730LBR |
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AD7730/AD7730L
–34–
REV. A
POWE R SUPPLIE S
T here is no specific power sequence required for the AD7730,
either the AV
DD
or the DV
DD
supply can come up first. While
the latch-up performance of the AD7730 is very good, it is
important that power is applied to the AD7730 before signals at
REF IN, AIN or the logic input pins in order to avoid latch-up
caused by excessive current. If this is not possible, the current
that flows in any of these pins should be limited to less than 30
mA per pin and less than 100 mA cumulative. If separate sup-
plies are used for the AD7730 and the system digital circuitry,
the AD7730 should be powered up first. If it is not possible to
guarantee this, current limiting resistors should be placed in
series with the logic inputs to again limit the current to less than
30 mA per pin and less than 100 mA total.
Grounding and Layout
Since the analog inputs and reference input are differential,
most of the voltages in the analog modulator are common-mode
voltages. T he excellent common-mode rejection of the part will
remove common-mode noise on these inputs. T he analog and
digital supplies to the AD7730 are independent and separately
pinned out to minimize coupling between the analog and digital
sections of the device. T he digital filter will provide rejection of
broadband noise on the power supplies, except at integer mul-
tiples of the modulator sampling frequency or multiples of the
chop frequency in chop mode. T he digital filter also removes
noise from the analog and reference inputs provided those noise
sources do not saturate the analog modulator. As a result, the
AD7730 is more immune to noise interference than a conven-
tional high resolution converter. However, because the resolu-
tion of the AD7730 is so high and the noise levels from the
AD7730 so low, care must be taken with regard to grounding
and layout.
T he printed circuit board that houses the AD7730 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. T his facilitates the use of
ground planes that can be easily separated. A minimum etch
technique is generally best for ground planes as it gives the best
shielding. Digital and analog ground planes should only be
joined in one place. If the AD7730 is the only device requiring
an AGND to DGND connection, the ground planes should
be connected at the AGND and DGND pins of the AD7730. If
the AD7730 is in a system where multiple devices require AGND
to DGND connections, the connection should still be made at
one point only, a star ground point that should be established as
closely as possible to the AD7730.
Avoid running digital lines under the device as these will couple
noise onto the die. T he analog ground plane should be allowed
to run under the AD7730 to avoid noise coupling. T he power
supply lines to the AD7730 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals such as
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. T races on opposite sides of the board should
run at right angles to each other. T his will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Good decoupling is important when using high resolution
ADCs. All analog supplies should be decoupled with 10
μ
F
tantalum in parallel with 0.1
μ
F ceramic capacitors to AGND.
T o achieve the best from these decoupling components, they
have to be placed as close as possible to the device, ideally right
up against the device. All logic chips should be decoupled with
0.1
μ
F disc ceramic capacitors to DGND. In systems where a
common supply voltage is used to drive both the AV
DD
and
DV
DD
of the AD7730, it is recommended that the system’s
AV
DD
supply is used. T his supply should have the recom-
mended analog supply decoupling capacitors between the AV
DD
pin of the AD7730 and AGND and the recommended digital
supply decoupling capacitor between the DV
DD
pin of the
AD7730 and DGND.
E valuating the AD7730 Performance
A recommended layout for the AD7730 is outlined in the evalu-
ation board for the AD7730. T he evaluation board package
includes a fully assembled and tested evaluation board, docu-
mentation, software for controlling the board over the printer
port of a PC and software for analyzing the AD7730’s perfor-
mance on the PC . T he evaluation board order number is
EVAL-AD7730EB.
Noise levels in the signals applied to the AD7730 may also
affect performance of the part. T he AD7730 allows two tech-
niques for evaluating the true performance of the part, indepen-
dent of the analog input signal. T hese schemes should be used
after a calibration has been performed on the part.
T he first method is to select the AIN1(–)/AIN1(–) input chan-
nel arrangement. In this case, the differential inputs to the
AD7730 are internally shorted together to provide a zero differ-
ential voltage for the analog modulator. External to the device,
the AIN1(–) input should be connected to a voltage which is
within the allowable common-mode range of the part.
T he second scheme is to evaluate the part with a voltage near
input full scale. T his can be achieved by again using input pair
AIN1(–), but by adding a differential voltage via the T ARE
DAC. T his allows the user to evaluate noise performance with a
near full-scale voltage.
T he software in the evaluation board package allows the user to
look at the noise performance in terms of counts, bits and nV.
Once the user has established that the noise performance of the
part is satisfactory in this mode, an external input voltage can
then be applied to the device incorporating more of the signal
chain.
相關PDF資料 |
PDF描述 |
|---|---|
| AD7730LBRU | Bridge Transducer ADC |
| AD7730 | Bridge Transducer ADC |
| AD7730BN | Bridge Transducer ADC |
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7730LBR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 600sps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.6KSPS 24BIT SERL 24SOIC W - Tape and Reel |
| AD7730LBR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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