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參數(shù)資料
| 型號： | AD7730LBR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 19/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730LBR |
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AD7730/AD7730L
REV. A
–19–
T able X V. SF Ranges
CHOP
0
1
0
1
SKIP
0
0
1
1
SF Range
2048 to 150
2048 to 75
2048 to 40
2048 to 20
Output Update Rate Range (Assuming 4.9152 MHz Clock)
150 Hz to 2.048 kHz
50 Hz to 1.365 kHz
150 Hz to 7.6 kHz
50 Hz to 5.12 kHz
Bit
Location
Bit
Mnemonic
Description
FR11–FR10
FR9
ZERO
SK IP
A zero
must
be written to these bits to ensure correct operation of the AD7730.
FIR Filter Skip Bit. With a 0 in this bit, the AD7730 performs two stages of filtering before
shipping a result out of the filter. T he first is a sinc
3
filter followed by a 22-tap FIR filter. With a
1 in this bit, the FIR filter on the part is bypassed and the output of the sinc
3
is fed directly
as the output result of the AD7730’s filter (see Filter Architecture for more details on the filter
implementation).
FAST
Step Mode Enable Bit. A 1 in this bit enables the
FAST
Step mode on the AD7730. In
this mode, if a step change on the input is detected, the FIR calculation portion of the filter is
suspended and replaced by a simple moving average on the output of the sinc
3
filter. Initially,
two outputs from the sinc
3
filter are used to calculate an AD7730 output. T he number of sinc
3
outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to 16) until
the
STDY
bit goes low. When the FIR filter has fully settled after a step, the
STDY
bit will
become active and the FIR filter is switched back into the processing loop (see Filter Architec-
ture section for more details on the
FAST
Step mode).
A zero
must
be written to these bits to ensure correct operation of the AD7730.
AC Excitation Bit. If the signal source to the AD7730 is ac-excited, a 1 must be placed in this
bit. For dc-excited inputs, this bit must be 0. T he ac bit has no effect if CHP is 0. With the ac
bit at 1, the AD7730 assumes that the voltage at the AIN(+)/AIN(–) and REF IN(+)/REF IN(–)
input terminals are reversed on alternate input sampling cycles (i.e. chopped). Note that when
the AD7730 is performing internal zero-scale or full-scale calibrations, the ac bit is treated as a
0, i.e., the device performs these self-calibrations with dc excitation.
Chop Enable Bit. T his bit determines if the chopping mode on the part is enabled. A 1 in this
bit location enables chopping on the part. When the chop mode is enabled, the part is effectively
chopped at its input and output to remove all offset and offset drift errors on the part. If offset
performance with time and temperature are important parameters in the design, it is recom-
mended that the user enable chopping on the part. If the input signal is dc-excited, the user has
the option of operating the part in either chop or nonchop mode. If the input signal is ac-excited,
both the ac bit and the CHP bit must be set to 1. T he chop rate on the ACX and
ACX
signals is
one half of the programmed output rate of the part and thus the chopping frequency varies with
the programmed output rate.
Delay Selection Bits. T hese four bits program the delay (in modulator cycles) to be inserted after
each chop edge when the CHP bit is 1. One modulator cycle is MCLK IN/16 and is 3.25
μ
s at
MCLK IN = 4.9152 MHz. A delay should only be required when in ac mode. Its purpose is to
cater for external delays between the switching signals (ACX and
ACX
) and when the analog
inputs are actually switched and settled. During the specified number of cycles (between 0 and
15), the modulator is held in reset and the filter does not accept any inputs. If CHP = 1, the
output rate is (MCLK IN/ 16
×
(DL + 3
×
SF) where DL is the value loaded to bits DL0–DL3.
T he chop rate is always one half of the output rate. T his chop period takes into account the
programmed delay and the fact that the sinc
3
filter must settle every chop cycle. With CHP = 0,
the output rate is 1/SF.
FR8
FAST
FR7–FR6
FR5
ZERO
AC
FR4
CHP
FR3–FR0
DL3–DL0
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| AD7730LBR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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