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參數(shù)資料
型號(hào): AD7730LBR
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Bridge Transducer ADC
中文描述: 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝: SOIC-24
文件頁(yè)數(shù): 39/52頁(yè)
文件大小: 497K
代理商: AD7730LBR
AD7730/AD7730L
REV. A
–39–
configured for continuous read operation when interfacing to
the 8X C51. T he serial clock on the 8X C51 idles high between data
transfers and therefore the POL input of the AD7730 should be
hardwired to a logic high. T he 8X C51 outputs the LSB first in a
write operation while the AD7730 expects the MSB first so the
data to be transmitted has to be rearranged before being written
to the output serial register. Similarly, the AD7730 outputs the
MSB first during a read operation while the 8X C51 expects the
LSB first. T herefore, the data read into the serial buffer needs to
be rearranged before the correct data word from the AD7730 is
available in the accumulator.
SYNC
RESET
AD7730
POL
DATA OUT
DATA IN
SCLK
CS
P3.0
P3.1
8XC51
DV
DD
Figure 21. AD7730 to 8XC51 Interface
AD7730 to ADSP-2103/ADSP-2105 Interface
Figure 22 shows an interface between the AD7730 and the
ADSP-2105 DSP processor. In the interface shown, the
RDY
bit of the Status Register is again monitored to determine when
the Data Register is updated. T he alternative scheme is to use
an interrupt driven system, in which case the
RDY
output is
connected to the
IRQ2
input of the ADSP-2105. T he
RFS
and
TFS
pins of the ADSP-2105 are configured as active low out-
puts and the ADSP-2105 serial clock line, SCLK , is also config-
ured as an output. T he POL pin of the AD7730 is hardwired
low. Because the SCLK from the ADSP-2105 is a continuous
clock, the
CS
of the AD7730 must be used to gate off the clock
once the transfer is complete. T he
CS
for the AD7730 is active
when either the
RFS
or
TFS
outputs from the ADSP-2105 are
active. T he serial clock rate on the ADSP-2105 should be lim-
ited to 3 MHz to ensure correct operation with the AD7730.
SYNC
RESET
AD7730
DATA OUT
DATA IN
SCLK
CS
DR
SCLK
ADSP-2105
DV
DD
RFS
TFS
DT
POL
Figure 22. AD7730 to ADSP-2105 Interface
相關(guān)PDF資料
PDF描述
AD7730LBRU Bridge Transducer ADC
AD7730 Bridge Transducer ADC
AD7730BN Bridge Transducer ADC
AD7730BR Bridge Transducer ADC
AD7730BRU Bridge Transducer ADC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AD7730LBRU-REEL7 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率(瓦特):- 電壓 - 電源,模擬:3 V ~ 3.6 V 電壓 - 電源,數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN(5x5) 包裝:帶卷 (TR)
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