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參數(shù)資料
| 型號： | AD7730LBR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 48/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730LBR |
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AD7730/AD7730L
–48–
REV. A
OUT PUT NOISE AND RE SOLUT ION SPE CIFICAT ION
T he AD7730L can be programmed to operate in either chop mode or nonchop mode. T he chop mode can be enabled in ac-excited
or dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. T hese
options are discussed in more detail in earlier sections. T he chop mode has the advantage of lower drift numbers and better noise
immunity, but the noise is approximately 20% higher for a given –3 dB frequency and output data rate. It is envisaged that the major-
ity of weigh-scale users of the AD7730L will operate the part in chop mode to avail themselves of the excellent drift performance and
noise immunity when chopping is enabled. T he following tables outline the noise performance of the part in both chop and nonchop
modes over all input ranges for a selection of output rates.
Output Noise (CHP = 1)
T his mode is the primary mode of operation of the device. T able X X I shows the output rms noise for some typical output update
rates and –3 dB frequencies for the AD7730 when used in chopping mode (CHP of Filter Register = 1) with a master clock
frequency of 2.4576 MHz. T hese numbers are typical and are generated at a differential analog input voltage of 0 V. T he output
update rate is selected via the SF0 to SF11 bits of the Filter Register. T able X X II, meanwhile, shows the output peak-to-peak resolu-
tion in counts for the same output update rates. T he numbers in brackets are the effective peak-to-peak resolution in bits (rounded to
the nearest 0.5 LSB). It is important to note that the numbers in T able X X II represent the resolution for which there will be no code
flicker within a six-sigma limit. T hey are not calculated based on rms noise, but on peak-to-peak noise.
T he numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in T able X X I will remain the same for unipolar ranges while the
numbers in T able II will change. T o calculate the numbers for T able X X II for unipolar input ranges simply divide the peak-to-peak
resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.
T able X X I. Output Noise vs. Input Range and Update Rate (CHP = 1)
T ypical Output RMS Noise in nV
Output
Data Rate Frequency
–3 dB
SF
Word
Settling T ime
Normal Mode
Settling T ime
Fast Mode
Input Range
=
6
80 mV
Input Range
=
6
40 mV
Input Range
=
6
20 mV
Input Range
=
6
10 mV
25 Hz
50 Hz
75 Hz
100 Hz*
200 Hz
0.98 Hz
1.97 Hz
2.96 Hz
3.95 Hz
7.9 Hz
2048
1024
683
512
256
920 ms
460 ms
306 ms
230 ms
115 ms
120 ms
60 ms
40 ms
30 ms
15 ms
245
340
420
500
650
140
220
270
290
490
105
160
170
180
280
70
100
110
130
165
*Power-On Default
T able X X II. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1)
Peak-to-Peak Resolution in Counts (Bits)
Output
Data Rate Frequency
–3 dB
SF
Word
Settling T ime
Normal Mode
Settling T ime
Fast Mode
Input Range
=
6
80 mV
Input Range
=
6
40 mV
Input Range
=
6
20 mV
Input Range
=
6
10 mV
25 Hz
50 Hz
75 Hz
100 Hz*
200 Hz
0.98 Hz
1.97 Hz
2.96 Hz
3.95 Hz
7.9 Hz
2048
1024
683
512
256
920 ms
460 ms
306 ms
230 ms
115 ms
120 ms
60 ms
40 ms
30 ms
15 ms
110k (17)
80k (16.5)
62k (16)
53k (15.5)
44k (15.5)
94k (16.5)
60k (16)
50k (15.5)
46k (15.5)
27k (15)
64k (16)
42k (15.5)
39k (15)
36k (15)
24k (14.5)
46k (15.5)
33k (15)
31k (15)
25k (14.5)
20k (14.5)
*Power-On Default
Output Noise (CHP = 0)
T able X X III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730L when used in
nonchopping mode (CHP of Filter Register = 0) with a master clock frequency of 2.4576 MHz. T hese numbers are typical and are
generated at a differential analog input voltage of 0 V. T he output update rate is selected via the SF0 to SF11 bits of the Filter Regis-
ter. T able X X IV, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. T he numbers in
brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in
T able X X IV represent the resolution for which there will be no code flicker within a six-sigma limit. T hey are not calculated based on
rms noise, but on peak-to-peak noise.
T he numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in T able X X III will remain the same for unipolar ranges while
the numbers in T able X X IV will change. T o calculate the number for T able X X IV for unipolar input ranges simply divide the peak-
to-peak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.
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| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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