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參數資料
| 型號： | AD7730LBR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 18/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730LBR |
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AD7730/AD7730L
–18–
REV. A
Bit
Location
MR2
Bit
Mnemonic
BO
Description
Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout currents
connect to the selected analog input pair, one source current to the AIN(+) input and one sink current to
the AIN(–) input. A 0 in this bit turns off the on-chip burnout currents.
MR1–MR0
CH1–CH0
Channel Selection Bits. T hese bits select the analog input channel to be converted or calibrated as
outlined in T able X III. With CH1 at 1 and CH0 at 0, the part looks at the AIN1(–) input internally
shorted to itself. T his can be used as a test method to evaluate the noise performance of the part with
no external noise sources. In this mode, the AIN1(–) input should be connected to an external voltage
within the allowable common-mode range of the part. T he Offset and Gain Calibration Registers on
the part are paired. T here are three pairs of calibration registers labelled Register Pair 0 through Regis-
ter Pair 2. T hese are assigned to the input channel pairs as outlined in T able X III.
T able X III. Channel Selection
Input Channel Pair
Positive Input
AIN1(+)
AIN2(+)
AIN1(–)
AIN1(–)
CH1
0
0
1
1
CH0
0
1
0
1
Negative Input
AIN1(–)
AIN2(–)
AIN1(–)
AIN2(–)
Calibration Register Pair
Register Pair 0
Register Pair 1
Register Pair 0
Register Pair 2
Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 200010 Hex
T he Filter Register is a 24-bit register from which data can be read or to which data can be written. T his register determines the
amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode and the delay
associated with chopping the inputs. T able X IV outlines the bit designations for the Filter Register. FR0 through FR23 indicate the
bit location, FR denoting the bits are in the Filter Register. FR23 denotes the first bit of the data stream. T he number in brackets
indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and
Figure 6 shows a flowchart for writing to the registers on the part.
T able X IV. Filter Register
FR23
FR22
FR21
FR20
FR19
FR18
FR17
FR16
SF11 (0)
SF10 (0)
SF9 (1)
SF8 (0)
SF7 (0)
SF6 (0)
SF5 (0)
SF4 (0)
FR15
FR14
FR13
FR12
FR11
FR10
FR9
FR8
SF3 (0)
SF2 (0)
SF1 (0)
SF0 (0)
ZERO (0)
ZERO (0)
SK IP (0)
FAST (0)
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
ZERO (0)
ZERO (0)
AC (0)
CHP (1)
DL3 (0)
DL2 (0)
DL1 (0)
DL0 (0)
Bit
Location
FR23–FR12
Bit
Mnemonic
SF11–SF0
Description
Sinc
3
Filter Selection Bits. T he AD7730 contains two filters: a sinc
3
filter and an FIR filter. T he 12 bits
programmed to SF11 through SF0 set the amount of averaging the sinc
3
filter performs. As a result,
the number programmed to these 12 bits affects the –3 dB frequency and output update rate from the
part (see Filter Architecture section). T he allowable range for SF words depends on whether the part
is operated with CHOP on or off and SK IP on or off. T able X V outlines the SF ranges for different
setups. All output update rates will be one-half those quoted in T able X V for the AD7730L operating
with a 2.4576 MHz clock.
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| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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