- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄373915 > AD7730LBR (ANALOG DEVICES INC) Bridge Transducer ADC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7730LBR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁(yè)數(shù)： | 33/52頁(yè) |
| 文件大?。?/td> | 497K |
| 代理商： | AD7730LBR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)當(dāng)前第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)
AD7730/AD7730L
REV. A
–33–
AD7730
CRYSTAL OR
CERAMIC
RESONATOR
C1
C2
MCLK IN
MCLK OUT
Figure 17. Crystal/Resonator Connections
T he on-chip oscillator circuit also has a start-up time associated
with it before it has attained its correct frequency and correct
voltage levels. T he typical start-up time for the circuit is 6 ms,
with a DV
DD
of +5 V and 8 ms with a DV
DD
of +3 V.
T he AD7730’s master clock appears on the MCLK OUT pin of
the device. T he maximum recommended load on this pin is one
CMOS load. When using a crystal or ceramic resonator to gen-
erate the AD7730’s clock, it may be desirable to then use this
clock as the clock source for the system. In this case, it is recom-
mended that the MCLK OUT signal is buffered with a CMOS
buffer before being applied to the rest of the circuit.
System Synchronization
T he
SYNC
input allows the user to reset the modulator and
digital filter without affecting any of the setup conditions on the
part. T his allows the user to start gathering samples of the ana-
log input from a known point in time, i.e., the rising edge of
SYNC
.
If multiple AD7730s are operated from a common master clock,
they can be synchronized to update their output registers simul-
taneously. A falling edge on the
SYNC
input resets the digital
filter and analog modulator and places the AD7730 into a con-
sistent, known state. While the
SYNC
input is low, the AD7730
will be maintained in this state. On the rising edge of
SYNC
,
the modulator and filter are taken out of this reset state and on
the next clock edge the part starts to gather input samples again.
In a system using multiple AD7730s, a common signal to their
SYNC
inputs will synchronize their operation. T his would nor-
mally be done after each AD7730 has performed its own cali-
bration or has had calibration coefficients loaded to it. T he
output updates will then be synchronized with the maximum
possible difference between the output updates of the individual
AD7730s being one MCLK IN cycle.
Single-Shot Conversions
T he
SYNC
input can also be used as a start convert command
allowing the AD7730 to be operated in a conventional converter
fashion. In this mode, the rising edge of
SYNC
starts conversion
and the falling edge of
RDY
indicates when conversion is com-
plete. T he disadvantage of this scheme is that the settling time
of the filter has to be taken into account for every data register
update.
Writing 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode regis-
ter has the same effect. T his initiates a single conversion on the
AD7730 with the part returning to idle mode at the end of
conversion. Once again, the full settling-time of the filter has to
elapse before the Data Register is updated.
Reset Input
T he
RESET
input on the AD7730 resets all the logic, the digital
filter and the analog modulator while all on-chip registers are
reset to their default state.
RDY
is driven high and the AD7730
ignores all communications to any of its registers while the
RESET
input is low. When the
RESET
input returns high, the
AD7730 starts to process data and
RDY
will return low after
the filter has settled indicating a valid new word in the data
register. However, the AD7730 operates with its default setup
conditions after a
RESET
and it is generally necessary to set up all
registers and carry out a calibration after a
RESET
command.
T he AD7730’s on-chip oscillator circuit continues to function
even when the
RESET
input is low. T he master clock signal
continues to be available on the MCLK OUT pin. T herefore, in
applications where the system clock is provided by the AD7730’s
clock, the AD7730 produces an uninterrupted master clock
during
RESET
commands.
Standby Mode
T he
STANDBY
input on the AD7730 allows the user to place
the part in a power-down mode when it is not required to pro-
vide conversion results. T he part can also be placed in its
standby mode by writing 0, 1, 1 to the MD2, MD1, MD0 bits
of the Mode Register. T he AD7730 retains the contents of all its
on-chip registers (including the Data Register) while in standby
mode. Data can still be read from the part in Standby Mode.
T he ST BY bit of the Status Register indicates whether the part
is in standby or normal operating mode. When the
STANDBY
pin is taken high, the part returns to operating as it had been
prior to the
STANDBY
pin going low.
T he
STANDBY
input (or 0, 1, 1 in the MD2, MD1, MD0 bits)
does not affect the digital interface. It does, however, set the
RDY
bit and pin high and also sets the
STDY
bit high. When
STANDBY
goes high again,
RDY
and
STDY
remain high until
set low by a conversion or calibration.
Placing the part in standby mode, reduces the total current to
10
μ
A typical when the part is operated from an external master
clock provided this master clock is stopped. If the external clock
continues to run in standby mode, the standby current increases
to 400
μ
A typical. If a crystal or ceramic resonator is used as the
clock source, then the total current in standby mode is 400
μ
A
typical. T his is because the on-chip oscillator circuit continues
to run when the part is in its standby mode. T his is important in
applications where the system clock is provided by the AD7730’s
clock, so that the AD7730 produces an uninterrupted master
clock even when it is in its standby mode.
Digital Outputs
T he AD7730 has two digital output pins, D0 and D1. When the
DEN bit of the Mode Register is set to 1, these digital outputs
assume the logic status of bits D0 and D1 of the Mode Register.
It gives the user access to two digital port pins which can be
programmed over the normal serial interface of the AD7730.
T he two outputs obtain their supply voltage from AV
DD
,
thus the outputs operate to 5 V levels even in cases where
DV
DD
= +3 V.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7730LBRU | Bridge Transducer ADC |
| AD7730 | Bridge Transducer ADC |
| AD7730BN | Bridge Transducer ADC |
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7730LBR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 600sps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.6KSPS 24BIT SERL 24SOIC W - Tape and Reel |
| AD7730LBR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。