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參數資料
| 型號： | AD7730LBR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 38/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730LBR |
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AD7730/AD7730L
–38–
REV. A
MICROCOMPUT E R/MICROPROCE SSOR INT E RFACING
T he AD7730’s flexible serial interface allows for easy interface
to most microcomputers and microprocessors. T he pseudo-code
of T able X IX and T able X X outline typical sequences for inter-
facing a microcontroller or microprocessor to the AD7730.
Figures 20, 21 and 22 show some typical interface circuits.
T he serial interface on the AD7730 has the capability of operat-
ing from just three wires and is compatible with SPI interface
protocols. T he three-wire operation makes the part ideal for
isolated systems where minimizing the number of interface lines
minimizes the number of opto-isolators required in the system.
Register lengths on the AD7730 vary from 8 to 16 to 24 bits.
T he 8-bit serial ports of most microcontrollers can handle
communication with these registers as either one, two or three
8-bit transfers. DSP processors and microprocessors generally
transfer 16 bits of data in a serial data operation. Some of these
processors, such as the ADSP-2105, have the facility to program
the amount of cycles in a serial transfer. T his allows the user to
tailor the number of bits in any transfer to match the register
length of the required register in the AD7730. In any case,
writing 32 bits of data to a 24-bit register is not an issue provided
the final eight bits of the word are all 1s. T his is because the
part returns to the Communications Register following a write
operation.
Even though some of the registers on the AD7730 are only eight
bits in length, communicating with two of these registers in
successive write operations can be handled as a single 16-bit
data transfer if required. For example, if the DAC Register is to
be updated, the processor must first write to the Communica-
tions Register (saying that the next operation is a write to the
Mode Register) and then write eight bits to the DAC Register.
T his can all be done in a single 16-bit transfer, if required, be-
cause once the eight serial clocks of the write operation to the
Communications Register have been completed, the part imme-
diately sets itself up for a write operation to the DAC Register.
AD7730 to 68HC11 Interface
Figure 20 shows an interface between the AD7730 and the
68HC11 microcontroller. T he diagram shows the minimum
(three-wire) interface with
CS
on the AD7730 hardwired low.
In this scheme, the
RDY
bit of the Status Register is monitored
to determine when the Data Register is updated. An alternative
scheme, which increases the number of interface lines to four, is
to monitor the
RDY
output line from the AD7730. T he moni-
toring of the
RDY
line can be done in two ways. First,
RDY
can
be connected to one of the 68HC11’s port bits (such as PC0),
which is configured as an input. T his port bit is then polled to
determine the status of
RDY
. T he second scheme is to use an
interrupt driven system, in which case the
RDY
output is con-
nected to the
IRQ
input of the 68HC11. For interfaces which
require control of the
CS
input on the AD7730, one of the port
bits of the 68HC11 (such as PC1), which is configured as an
output, can be used to drive the
CS
input.
T he 68HC11 is configured in the master mode with its CPOL
bit set to a logic zero and its CPHA bit set to a logic one. When
the 68HC11 is configured like this, its SCL K line idles low
between data transfers. T herefore, the POL input of the AD7730
should be hardwired low. For systems where it is preferable that
the SCLK idle high, the CPOL bit of the 68HC11 should be set
to a Logic 1 and the POL input of the AD7730 should be hard-
wired to a logic high.
T he AD7730 is not capable of full duplex operation. If the
AD7730 is configured for a write operation, no data appears on
the DAT A OUT lines even when the SCLK input is active.
When the AD7730 is configured for continuous read operation,
data presented to the part on the DAT A IN line is monitored to
determine when to exit the continuous read mode.
SYNC
RESET
AD7730
SCLK
DATA OUT
DATA IN
CS
POL
SS
SCK
MISO
MOSI
68HC11
DV
DD
DV
DD
Figure 20. AD7730 to 68HC11 Interface
AD7730 to 8051 Interface
An interface circuit between the AD7730 and the 8X C51 mi-
crocontroller is shown in Figure 21. T he diagram shows the
minimum number of interface connections with
CS
on the
AD7730 hardwired low. In the case of the 8X C51 interface, the
minimum number of interconnects is just two. In this scheme,
the
RDY
bit of the Status Register is monitored to determine
when the Data Register is updated. T he alternative scheme,
which increases the number of interface lines to three, is to
monitor the
RDY
output line from the AD7730. T he monitor-
ing of the
RDY
line can be done in two ways. First,
RDY
can be
connected to one of the 8X C51’s port bits (such as P1.0), which
is configured as an input. T his port bit is then polled to deter-
mine the status of
RDY
. T he second scheme is to use an inter-
rupt driven system, in which case the
RDY
output is connected
to the
INT1
input of the 8X C51. For interfaces that require
control of the
CS
input on the AD7730, one of the port bits of
the 8X C51 (such as P1.1), which is configured as an output,
can be used to drive the
CS
input.
T he 8X C51 is configured in its Mode 0 serial interface mode.
Its serial interface contains a single data line. As a result, the
DAT A OUT and DAT A IN pins of the AD7730 should be
connected together. T his means that the AD7730 must not be
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