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參數(shù)資料
| 型號(hào)： | AD9866BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大小： | 1647K |
| 代理商： | AD9866BCP |
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AD9866
Rev. 0 | Page 20 of 48
Power-Up Default Value
MODE = 0 (Half-Duplex)
CONFIG = 0
MODE = 1 (Full-Duplex)
CONFIG = 0
Address
(Hex)
1
Rx PATH CONTROL
0x07
Bit
Break-
down
Description
Width
CONFIG = 1
CONFIG = 1
Comments
(5)
(4)
(0)
Initiate Offset Cal.
Rx Low Power
Rx Filter ON
1
1
1
0
0
1
0
1*
1
0
0
1
0
1*
1
Default setting has LPF ON
and Rx path at nominal
power bias setting.
*Rx path to low power.
Refer to Low-Pass Filter
section.
0x08
(7:0)
Rx Filter Tuning
Cut-off Frequency
8
0x80
0x61*
0x80
0x80
Tx/Rx PATH GAIN CONTROL
0x09
(6)
(5:0)
Use SPI Rx Gain
Rx Gain Code
1
6
0x00
0x00
0x00
0x00
Default setting is for
hardware Rx gain code via
PGA or Tx data port.
Default setting is for Tx gain
code via SPI control.
0x0A
Tx AND Rx PGA CONTROL
0x0B
(6)
(5)
(3)
(2)
(1)
(6)
(5:0)
Use SPI Tx Gain
Tx Gain Code
1
6
0x7F
0x7F
0x7F
0x7F
PGA Code for Tx
PGA Code for Rx
Force GAIN strobe
Rx Gain on Tx Port
3-Bit RxPGA Port
1
1
1
1
1
0
1
0
0
0
0
1
0
0
1**
0
1
0
1*
0
0
1
0
1*
0
Default setting is RxPGA
control active.
*Tx port with GAIN strobe
(AD9875/AD9876
compatible).
** 3-bit RxPGA gain map
(AD9975 compatible).
Tx DIGITAL FILTER AND INTERFACE
0x0C
(7:6)
Interpolation
Factor
Invert
TXEN/TXSYNC
LS Nibble First*
TXCLK neg. edge
Twos complement
2
01
00
01
01
(4)
1
0
0
0
0
(2)
(1)
(0)
1
1
1
N/A
0
0
N/A
0
0
0
0
1
0
0
1
Default setting is 2×
interpolation with LPF
response. Data format is
straight binary for half-
duplex and twos
complement for full-duplex
interface.
*Full-duplex only.
Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK
0x0D
(7)
Analog Loopback
(6)
Digital Loopback*
(5)
Rx Port 3-State
(4)
Invert
RXEN/RXSYNC
(2)
LS Nibble First*
(1)
RXCLK neg. edge
(0)
Twos complement
DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID
0x0E
(7)
Low Drive
Strength
(0)
TxDAC Output
0x0F
(3:0)
REV ID Number
Tx IAMP GAIN AND BIAS CONTROL
0x10
(7)
Select Tx Gain
(6:4)
G1
(2:0)
N
0x11
(6:4)
G2
(2:0)
G3
1
1
1
1
0
0
N/A
0
0
0
N/A
0
0
0
0
0
0
0
0
0
1
1
1
N/A
0
0
N/A
0
0
0
0
1
0
0
1
Data format is straight
binary for half-duplex and
twos complement for full-
duplex interface.
Analog loopback: ADC Rx
data fed back to TxDAC.
Digital loopback: Tx input
data to Rx output port.
*Full-duplex only.
1
0
0
0
0
1
4
0
0x00
0
0x00
0
0x00
0
0x00
Default setting is for high
drive strength and IAMP
enabled.
1
3
3
3
3
0x44
0x44
0x44
0x44
Secondary path G1 = 0, 1, 2,
3, 4.
Primary path N = 0, 1, 2, 3, 4.
0x62
0x62
0x62
0x62
Secondary path stages:
G2 = 0 to 1.50 in 0.25 steps
and G3 = 0 to 6.
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| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
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