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參數資料
| 型號： | AD9866BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數： | 26/48頁 |
| 文件大小： | 1647K |
| 代理商： | AD9866BCP |
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AD9866
Rev. 0 | Page 26 of 48
0
6-BIT DIGITAL WORD-DECIMAL EQUIVALENT
G
0
48
24
60
66
–12
–6
0
6
12
18
24
30
36
42
54
42
48
30
36
6
12
18
Figure 56. Digital Gain Mapping of RxPGA
Table 15. SPI Registers RxPGA Control
Address (Hex)
Bit
0x09
(6)
(5:0)
0x0B
(6)
(5)
(3)
Description
Enable RxPGA update via SPI
RxPGA gain code
Select TxPGA via PGA[5:0]
Select RxPGA via PGA[5:0]
Enable software GAIN strobe –
full-duplex
Enable RxPGA update via Tx[5:0] –
full-duplex
3-bit RxPGA gain mapping –
half-duplex
(2)
(1)
The RxPGA gain register can be updated via the Tx[5:0] port,
the PGA[5:0] port, or the SPI port. The first two methods allow
fast updates of the RxPGA gain register and should be
considered for digital AGC functions requiring a fast closed-
loop response. The SPI port allows direct update and readback
of the RxPGA gain register via Reg. 0x09 with an update rate
limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6 of
Reg. 0x09 must be set for a read or write operation.
Updating the RxPGA via the Tx[5:0] port is an option only in
full-duplex mode.
1
In this case, a high level on the GAIN pin
2
with Tx SYNC low programs the PGA setting on either the
rising edge or falling edge of RXCLK, as shown in Figure 57.
The GAIN pin must be held high, TxSYNC must be held low,
and GAIN data must be stable for one or more clock cycles to
update the RxPGA gain setting. A low level on the GAIN pin
enables data to be fed to the digital interpolation filter. This
interface should be considered when upgrading existing designs
from the AD9876 MxFE product or half-duplex applications
trying to minimize an ASIC’s pin count.
1
Default setting for full-duplex mode (MODE = 1) .
2
The GAIN strobe can also be set in software via Reg. 0x0B, Bit 3 for
continuous updating. This eliminates the requirement for external GAIN
signal, reducing the ASIC pin count by 1.
t
SU
RXCL
K
Tx
SYNC
Tx [5:0
]
t
HD
GAIN
GAIN
0
Figure 57. Updating RxPGA via Tx[5:0] in Full-Duplex Mode
Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an
option for both the half-duplex
3
and full-duplex interfaces. The
PGA port consists of an input buffer that passes the 6-bit data
appearing at its input directly to the RxPGA (or TxPGA) gain
register with no gating signal required. Bit 5 or Bit 6 of Reg.
0x0B is used to select whether the data updates the RxPGA or
TxPGA gain register. In applications that switch between
RxPGA and TxPGA gain control via PGA[5:0], be careful that
the RxPGA (or TxPGA) is not inadvertently loaded with the
wrong data during a transition. In the case of an RxPGA to
TxPGA transition, first deselect the RxPGA gain register, update
the PGA[5:0] port with the desired TxPGA gain setting, and
then select the TxPGA gain register.
The RxPGA also offers an alternative 3-bit word gain mapping
option
4
that provides a 12 dB to +36 dB span in 8 dB incre-
ments as shown in Table 16. The 3-bit word is directed to
PGA[5:3] with PGA[5] being the MSB. This feature is backward
compatible with the AD9975 MxFE and allows direct interfac-
ing to the CX11647 or INT5130 HomePlug 1.0 PHYs.
Table 16. PGA Timing for AD9975 Backward Compatible
Mode
Digital Gain Setting
PGA[5:3]
Decimal
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Gain (dB)
12
12
4
4
12
20
28
36
3
Default setting for half-duplex mode (MODE = 0).
4
Default setting for MODE = 0 and CONFIG =1.
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| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
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