- 您現在的位置：買賣IC網 > PDF目錄373969 > AD9866BCP (ANALOG DEVICES INC) Broadband Modem Mixed Signal Front End PDF資料下載
參數資料
| 型號： | AD9866BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數： | 35/48頁 |
| 文件大小： | 1647K |
| 代理商： | AD9866BCP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
AD9866
Rev. 0 | Page 35 of 48
0
TARGET-DECIMAL EQUIVALENT
F
48
128
224
192
96
112
176
80
64
35
15
17
19
21
23
25
27
29
31
33
144
160
208
50 MSPS CALCULATED
80 MSPS CALCULATED
50 MSPS MEASURED
80 MSPS MEASURED
Figure 73. Measured and Calculated f
3 dB
vs. Target Value
for f
ADC
= 50 MSPS and 80 MSPS
The following scaling factor can be applied to the previous
formula to compensate for the RxPGA gain setting on f
3 dB
:
382
/
(
1
dB
in
RxPGA
Factor
Scale
=
Equation 9.
This scaling factor reduces the calculated f
3 dB
as the RxPGA is
increased. Applications that need to maintain a minimum cut-
off frequency, f
3 dB_MIN
, for all RxPGA gain settings should first
determine the scaling factor for the highest RxPGA gain setting
to be used. Next, the f
3 dB_MIN
should be divided by this scale
factor to normalize to the 0 dB RxPGA gain setting (f
3 dB_0 dB
).
Equation 8 can then be used to calculate the target
value.
The LPF frequency response shows a slight sensitivity to
temperature, as shown in Figure 74. Applications sensitive to
temperature drift can recalibrate the LPF by rewriting the target
value to Reg. 0x08.
0
TARGET-DECIMAL EQUIVALENT
F
96
128
240
192
176
112
35
15
20
25
30
144
160
208
F
OUT
ACTUAL 80MHz AND –40
°
C
224
F
OUT
ACTUAL 80MHz AND +25
°
C
F
OUT
ACTUAL 80MHz AND +85
°
C
Figure 74. Temperature Drift of f
3 dB
for f
ADC
= 80 MSPS and RxPGA = 0 dB
ANALOG TO DIGITAL CONVERTER (ADC)
The AD9866 features a 12-bit analog-to-digital converter
(ADC) capable of up to 80 MSPS. Referring to Figure 68, the
ADC is driven by the SPGA stage, which performs both the
sample-and-hold and the fine gain adjust functions. A buffer
amplifier (not shown) isolates the last CPGA gain stage from
the dynamic load presented by the SPGA stage. The full-scale
input span of the ADC is 2 V p-p, with the full-scale input span
into the SPGA adjustable from 1 V to 2 V in 1 dB increments,
depending on the PGA gain setting.
A pipelined multistage ADC architecture is used to achieve high
sample rates while consuming low power. The ADC distributes
the conversion over several smaller A/D subblocks, refining the
conversion with progressively higher accuracy as it passes the
results from stage to stage on each clock edge. The ADC
typically performs best when driven internally by a 50% duty
cycle clock. This is especially the case when operating the ADC
at high sample rate (55 MSPS to 80 MSPS) and/or lower
internal bias levels, which adversely affect interstage settling
time requirements.
The ADC sampling clock path also includes a duty cycle
restorer circuit, which ensures that the ADC gets a near 50%
duty cycle clock even when presented with a clock source with
poor symmetry (35/65). This circuit should be enabled, if the
ADC sampling clock is a buffered version of the reference
signal appearing at OSCIN (see the Clock Synthesizer section)
and if this reference signal is derived from an oscillator or
crystal whose specified symmetry cannot be guaranteed to be
within 45/55 (or 55/45). This circuit can remain disabled, if the
ADC sampling clock is derived from a divided down version of
the clock synthesizer’s VCO, because this clock is near 50%.
The ADC’s power consumption can be reduced by 25 mA, with
minimal effect on its performance, by setting Bit 4 of Reg. 0x07.
Alternative power bias settings are also available via Reg. 0x13,
as discussed in the Power Control and Dissipation section.
Lastly, the ADC can be completely powered down for half-
duplex operation, further reducing the AD9866’s peak power
consumption.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9870 | IF Digitizing Subsystem |
| AD9870EB | IF Digitizing Subsystem |
| AD9873 | Analog Front End Converter for Set-Top Box, Cable Modem |
| AD9873-EB | Analog Front End Converter for Set-Top Box, Cable Modem |
| AD9873JS | Analog Front End Converter for Set-Top Box, Cable Modem |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
| AD9866-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk |
發布緊急采購，3分鐘左右您將得到回復。