- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373969 > AD9866BCP (ANALOG DEVICES INC) Broadband Modem Mixed Signal Front End PDF資料下載
參數(shù)資料
| 型號： | AD9866BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 1647K |
| 代理商： | AD9866BCP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
AD9866
DIGITAL INTERFACE
The digital interface port is configurable for half-duplex or full-
duplex operation by pin-strapping the MODE pin low or high,
respectively. In half-duplex mode, the digital interface port
becomes a 10-bit bidirectional bus called the ADIO port. In full-
duplex mode, the digital interface port is divided into two 6-bit
ports called Tx[5:0] and Rx[5:0] for simultaneous Tx and Rx
operations. In this mode, data is transferred between the ASIC
and AD9866 in 6-bit nibbles. The AD9866 also features a
flexible digital interface for updating the RxPGA and TxPGA
gain registers via a 6-bit PGA port or Tx[5:0] port for fast
updates, or via the SPI port for slower updates. See the RXPGA
Control section.
Rev. 0 | Page 23 of 48
HALF-DUPLEX MODE
The half-duplex mode functions as follows when the MODE
pin is tied low. The bidirectional ADIO port is typically shared
in burst fashion between the transmit path and receive path.
Two control signals, TXEN and RXEN, from a DSP (or digital
ASIC) control the bus direction by enabling the ADIO port’s
input latch and output driver, respectively. Two clock signals,
TXCLK and RXCLK, are used to latch the Tx input data and
clock the Rx output data, respectively. The ADIO port can also
be disabled by setting TXEN and RXEN low (default setting),
thus allowing it to be connected to a shared bus.
Internally, the ADIO port consists of an input latch for the Tx
path in parallel with an output latch with three-state outputs for
the Rx path. TXEN is used to enable the input latch; RXEN is
used to three-state the output latch. A five-sample-deep FIFO is
used on the Tx and Rx paths to absorb any phase difference
between the AD9866’s internal clocks and the externally
supplied clocks (TXCLK, RXCLK). The ADIO bus accepts input
data-words into the transmit path when the TXEN pin is high,
the RXEN pin is low, and a clock is present on the TXCLK pin,
as shown in Figure 49.
TXCLK
TXEN
ADIO[9:0]
RXEN
TX0
TX2
TX3
TX4
TX1
t
DIS
0
t
DH
t
EN
t
DS
Figure 49. Transmit Data Input Timing Diagram
The Tx interpolation filter(s) following the ADIO port can be
flushed with zeros, if the clock signal into the TXCLK pin is
present for 33 clock cycles after TXEN goes low. Note that the
data on the ADIO bus is irrelevant over this interval.
The output from the receive path is driven onto the ADIO bus
when the RXEN pin is high, and a clock is present on the
RXCLK pin. While the output latch is enabled by RXEN, valid
data appears on the bus after a 6-clock-cycle delay due to the
internal FIFO delay. Note that Rx data is not latched back into
the Tx path, if TXEN is high during this interval with TXCLK
present. The ADIO Bus becomes three-stated once the RXEN
pin returns low. Figure 50 illustrates the receive path output
timing.
t
PZL
0
RXEN
ADIO[9:0]
RXCLK
t
VT
t
PLZ
t
OD
RX0
RX1
RX2
RX3
Figure 50. Receive Data Output Timing Diagram
To add flexibility to the digital interface port, several program-
ming options are available in the SPI registers. These options are
listed in Table 13. The default Tx and Rx data input formats are
straight binary, but can be changed to twos complement. The
default TXEN and RXEN settings are active high, but can be set
to opposite polarities, thus allowing them to share the same
control. In this case, the ADIO port can still be placed onto a
shared bus by disabling its input latch via the control signal, and
disabling the output driver via the SPI register. The clock timing
can be independently changed on the transmit and receive
paths by selecting either the rising or falling clock edge as the
validating/sampling edge of the clock. Lastly, the output driver’s
strength can be reduced for lower data rate applications.
Table 13. SPI Registers for Half-Duplex Interface
Address (Hex)
Bit
Description
0x0C
(4)
Invert TXEN
(1)
TXCLK negative edge
(0)
Twos complement
0x0D
(5)
Rx port three-state
(4)
Invert RXEN
(1)
RXCLK negative edge
(0)
Twos complement
0x0E
(7)
Low digital drive strength
The half-duplex interface can be configured to act like a slave or
a master to the digital ASIC. An example of a slave configura-
tion is shown in Figure 51. In this example, the AD9866 accepts
all the clock and control signals from the digital ASIC. Because
the sampling clocks for the DAC and ADC are derived inter-
nally from the OSCIN signal, it is required that the TXCLK and
RXCLK signals be at exactly the same frequency as the OSCIN
signal. The phase relationships among the TXCLK, RXCLK, and
OSCIN signals can be arbitrary. If the digital ASIC cannot
provide a low jitter clock source to OSCIN, consider using the
AD9866 to generate the clock for its DAC and ADC and pass
the desired clock signal to the digital ASIC via CLKOUT1 or
CLKOUT2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9870 | IF Digitizing Subsystem |
| AD9870EB | IF Digitizing Subsystem |
| AD9873 | Analog Front End Converter for Set-Top Box, Cable Modem |
| AD9873-EB | Analog Front End Converter for Set-Top Box, Cable Modem |
| AD9873JS | Analog Front End Converter for Set-Top Box, Cable Modem |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
| AD9866-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。