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參數資料
| 型號： | AD9866BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數： | 22/48頁 |
| 文件大小： | 1647K |
| 代理商： | AD9866BCP |
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AD9866
Rev. 0 | Page 22 of 48
SCLK
SDATA
SCLK
SDATA
R/W
N1
A1
A2
A3
A4
A0
N2
D71D61
D1N D0N
R/W
N1
A1
A2
A3
A4
A0
N2
D01D11
D7N
D6N
0
DATA TRANSFER CYCLE
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
INSTRUCTION CYCLE
SEN
SEN
Figure 45. SPI Timing, MSB First (Upper) and LSB First (Lower)
When the SPI LSB first bit is set high, the serial port interprets
both instruction and data bytes LSB first. Multibyte data
transfers in LSB format can be completed by writing an
instruction byte that includes the register address of the first
address to be accessed. The AD9866 automatically increments
the address for each successive byte required for the multibyte
communication cycle.
Figure 46 illustrates the timing requirements for a write
operation to the SPI port. After the serial port enable (SEN)
signal goes low, data (SDIO) pertaining to the instruction
header is read on the rising edges of the clock (SCLK). To
initiate a write operation, the read/not-write bit is set low. After
the instruction header is read, the eight data bits pertaining to
the specified register are shifted into the SDIO pin on the rising
edge of the next eight clock cycles. If a multibyte communica-
tion cycle is specified, the destination address is decremented
(MSB first) and another eight bits of data are shifted in. This
process repeats itself until all the bytes specified in the instruc-
tion header (N1, N0 bits) are shifted in. SEN must remain low
during the data transfer operation, only going high after the last
bit is shifted in.
D7
D6
A0
D1
SEN
N1
N0
t
S
SCLK
SDIO
1/
f
SCLK
t
LOW
t
HI
t
DS
t
DH
R/W
D0
t
H
0
Figure 46. SPI Write Operation Timing
Figure 47 illustrates the timing for a 3-wire read operation to
the SPI port. After SEN goes low, data (SDIO) pertaining to the
instruction header is read on the rising edges of SCLK. A read
operation occurs if the read/not-write indicator is set high.
After the address bits of the instruction header are read, the
eight data bits pertaining to the specified register are shifted out
of the SDIO pin on the falling edges of the next eight clock
cycles. If a multibyte communication cycle is specified in the
instruction header, a similar process as previously described for
a multibyte SPI write operation applies. The SDO pin remains
three-stated in a 3-wire read operation.
D7
D6
A0
D1
SEN
N1
t
S
SCLK
SDIO
1/
f
SCLK
t
LOW
t
HI
t
DS
t
DH
R/W
D0
t
EZ
A2
A1
t
DV
0
Figure 47. SPI 3-Wire Read Operation Timing
Figure 48 illustrates the timing for a 4-wire read operation to
the SPI port. The timing is similar to the 3-wire read operation
with the exception that data appears at the SDO pin, while the
SDIO pin remains high impedance throughout the operation.
The SDO pin is an active output only during the data transfer
phase and remains three-stated at all other times.
A0
SEN
N1
t
S
SCLK
SDIO
1/
f
SCLK
t
LOW
t
HI
t
DS
t
DH
R/W
t
EZ
A2
A1
t
DV
D7
D6
D1
SDO
D0
t
EZ
0
Figure 48. SPI 4-Wire Read Operation Timing
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
| AD9866-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk |
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