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參數(shù)資料
| 型號： | AD9866BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大小： | 1647K |
| 代理商： | AD9866BCP |
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AD9866
Rev. 0 | Page 24 of 48
TO
Tx DIGITAL
FILTER
12
ADIO
[11:0]
OSCIN
RXEN
TXEN
AD9866
FROM
Rx ADC
12
RXEN
TXEN
TXCLK
RXCLK
DAC_CLK
ADC_CLK
CLKOUT
DIGITAL ASIC
0
Tx/Rx
Data[11:0]
Figure 51. Example of a Half -Duplex Digital Interface
with AD9866 Serving as the Slave
Figure 52 shows a half-duplex interface with the AD9866 acting
as the master, generating all the required clocks. CLKOUT1
provides a clock equal to the bus data rate that is fed to the
ASIC as well as back to the TXCLK and RXCLK inputs. This
interface has the advantage of reducing the digital ASIC’s pin
count by three. The ASIC needs only to generate a bus control
signal that controls the data flow on the bidirectional bus.
TO
Tx DIGITAL
FILTER
12
ADIO
[11:0]
Tx/Rx
Data[11:0]
CLKOUT1
AD9866
FROM
Rx ADC
12
RXEN
TXEN
BUS_CTR
TXCLK
RXCLK
CLKIN
DIGITAL ASIC
0
OSCIN
FROM
CRYSTAL
OR MASTER CLK
Figure 52. Example of a Half -Duplex Digital Interface
with AD9866 Serving as the Master
FULL-DUPLEX MODE
The full-duplex mode interface is selected when the MODE pin
is tied high. It can be used for full- or half-duplex applications.
The digital interface port is divided into two 6-bit ports called
Tx[5:0] and Rx[5:0], allowing simultaneous
Tx and Rx opera-
tions for full-duplex applications. In half-duplex applications,
the Tx[5:0] port can also be used to provide a fast update of the
RxPGA (AD9876 backward compatible) during an Rx
operation. This feature is enabled by default and can be used to
reduce the required pin count of the ASIC (refer to RxPGA
Control section for more detail).
In either application, Tx and Rx data are transferred between
the ASIC and AD9866 in 6-bit (or 5-bit) nibbles at twice
the
internal input/output word rates of the Tx interpolation filter
and ADC. Note that the TxDAC update rate
must not
be less
than the nibble rate. Therefore, the 2× or 4× interpolation filter
must be used with a full-duplex interface.
The AD9866 acts as the master, providing RXCLK as an output
clock that is used for the timing of both the Tx[5:0] and Rx[5:0]
ports. RXCLK always runs at the nibble rate and can be inverted
or disabled via an SPI register. Because RXCLK is derived from
the clock synthesizer, it remains active, provided that this
functional block remains powered on. A buffered version of the
signal appearing at OSCIN can also be directed to RXCLK by
setting Bit 2 of Reg. 0x05. This feature allows the AD9866 to be
completely powered down (including the clock synthesizer)
while serving as the master.
The Tx[5:0] port operates in the following manner with the SPI
register default settings. Two consecutive nibbles of the Tx data
are multiplexed together to form a 10-bit data-word in twos
complement format. The clock appearing on the RXCLK pin is
a buffered version of the internal clock used by the Tx[5:0]
port’s input latch with a frequency that is always twice the ADC
sample rate (2 × f
ADC
). Data from the Tx[5:0] port is read on the
rising
edge of this sampling clock, as illustrated in the timing
diagram shown in Figure 53.
Tx 2 LSB
Tx3LSB
Tx0LSB
t
HD
t
DS
RXCLK
TxSYNC
Tx[5:0]
0
Tx1MSB
Tx1LSB
Tx2MSB
Tx3MSB
Figure 53. Tx[5:0] Port Full-Duplex Timing Diagram
The TXSYNC signal is used to indicate to which word a nibble
belongs. The first nibble of every word is read while TXSYNC is
low as the most significant nibble. The second nibble of that
same word is read on the following TXSYNC high level as the
least significant nibble. If TXSYNC is low for more than one
clock cycle, the last transmit data is read continuously until
TXSYNC is brought high for the second nibble of a new
transmit word. This feature can be used to flush the interpolator
filters with zeros. Note that the GAIN signal must be kept low
during a Tx operation.
The Rx[5:0] port operates in the following manner with the SPI
register default settings. Two consecutive nibbles of the Rx data
are multiplexed together to form a 10-bit data-word in twos
complement format. The Rx data is valid on the rising edge of
RXCLK, as illustrated in the timing diagram shown in
Figure 54. The RXSYNC signal is used to indicate to which
word a nibble belongs. The first nibble of every word is
transmitted while RXSYNC is low as the most significant
nibble. The second nibble of that same word is transmitted on
the following RXSYNC high level as the least significant nibble.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
| AD9866-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk |
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