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參數(shù)資料
| 型號(hào)： | AD9866BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁(yè)數(shù)： | 7/48頁(yè) |
| 文件大小： | 1647K |
| 代理商： | AD9866BCP |
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AD9866
SERIAL PORT TIMING SPECIFICATIONS
Table 5. AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted
Parameter
WRITE OPERATION (See Figure 46)
SCLK Clock Rate (f
SCLK
)
SCLK Clock High (t
HI
)
SCLK Clock Low (t
LOW
)
SDIO to SCLK Setup Time (t
DS
)
SCLK to SDIO Hold Time (t
DH
)
SEN to SCLK Setup Time (t
S
)
SCLK to SEN Hold Time (t
H
)
READ OPERATION (See Figure 47 and Figure 48)
SCLK Clock Rate (f
SCLK
)
SCLK Clock High (t
HI
)
SCLK Clock Low (t
LOW
)
SDIO to SCLK Setup Time (t
DS
)
SCLK to SDIO Hold Time (t
DH
)
SCLK to SDIO (or SDO) Data Valid Time (t
DV
)
SEN to SDIO Output Valid to Hi-Z (t
EZ
)
Rev. 0 | Page 7 of 48
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
14
14
14
0
14
0
14
14
14
0
Typ
2
Max
32
32
14
Unit
MHz
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
Table 6. AVDD = 3.3 V ±5%, DVDD = CLKVDD = DRVDD = 3.3 V ±10%, unless otherwise noted
Parameter
READ OPERATION (See Figure 50)
Output Data Rate
Three-State Output Enable Time (t
PZL
)
Three-State Output Disable Time (t
PLZ
)
Rx Data Valid Time (t
DV
)
Rx Data Output Delay (t
OD
)
WRITE OPERATION (See Figure 49)
Input Data Rate (1× Interpolation)
Input Data Rate (2× Interpolation)
Input Data Rate (4× Interpolation)
Tx Data Setup Time (t
DS
)
Tx Data Hold Time (t
DH
)
Latch Enable Time (t
EN
)
Latch Disable Time (t
DIS
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
II
II
II
II
II
II
II
II
II
II
II
II
Min
5
80
3
3
4
20
10
5
12.5
0
3
3
Typ
Max
80
80
80
50
Unit
MSPS
ns
ns
ns
ns
MSPS
MSPS
MSPS
ns
ns
ns
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
| AD9866-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk |
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