- 您現在的位置：買賣IC網 > PDF目錄373970 > AD9923ABBCZ (ANALOG DEVICES INC) CCD Signal Processor with V-Driver and Precision Timing⑩ Generator PDF資料下載
參數資料
| 型號： | AD9923ABBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 20/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
AD9923A
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 26 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions are used to designate the start and end
positions of the blanking period. Additionally, there is a polarity
control register, HBLKMASK, that designates the polarity of the
horizontal clock signals during the blanking period. Setting
HBLKMASK high sets H1 = H3 = high and H2 = H4 = low
during blanking, as shown in Figure 27. As with CLPOB and
PBLK registers, HBLK registers are available in each V-sequence,
allowing different blanking signals to be used with different
vertical timing sequences.
Rev. 0 | Page 20 of 88
Generating Special HBLK Patterns
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the
standard HBLK interval. However, additional toggle positions
can be used to generate special HBLK patterns, as shown in
Figure 28. The pattern in this example uses all six toggle
positions to generate two extra groups of pulses during the
HBLK interval. By changing the toggle positions, different
patterns can be created.
Table 12. HBLK Pattern Registers
Length
(Bits)
HBLKMASK
1
HBLKALT
3
Register
Range
High/low
0 to 7 alternation
modes
Description
Masking polarity for H1, H3, HL (0 = mask low, 1 = mask high)
Enables different odd/even alternation of HBLK toggle positions
0: disable alternation (HBLKTOGE1 to HBLKTOGE6 registers are used for each line)
1: TOGE1 and TOGE2 odd lines, TOGE3 to TOGE6 even lines
2: TOGE1 and TOGE2 even lines, TOGE3 to TOGE6 odd lines
3: TOGE1 to TOGE6 even lines, TOGO1 to TOGE6 odd lines (FREEZE/RESUME not
available)
4 to 7: HBLKSTART, HBLKEND, HBLKLEN, and HBLKREP registers are used for each line
HBLK first toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE1
13
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixels
0 to 255 repetitions
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixel
location
0 to 8191 pixel
location
HBLKTOGE2
13
HBLK second toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE3
13
HBLK third toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE4
13
HBLK fourth toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE5
13
Fifth toggle position, even lines (HBLKSTART when HBLKALT = 4 to 7)
HBLKTOGE6
13
Sixth toggle position, even lines (HBLKEND when HBLKALT = 4 to 7)
HBLKLEN
HBLKREP
HBLKTOGO1 13
13
8
HBLK pattern length, only used when HBLKALT = 4 to 7
Number of HBLK pattern repetitions, only used when HBLKALT = 4 to 7
First toggle position for odd lines when HBLKALT = 3 (usually VREPA_3)
HBLKTOGO2 13
Second toggle position for odd lines when HBLKALT = 3 (usually VREPA_4)
HBLKTOGO3 13
Third toggle position for odd lines when HBLKALT = 3 (usually FREEZE1)
HBLKTOGO4 13
Fourth toggle position for odd lines when HBLKALT = 3 (usually RESUME1)
HBLKTOGO5 13
Fifth toggle position for odd lines when HBLKALT = 3 (usually FREEZE2)
HBLKTOGO6 13
Sixth toggle position for odd lines when HBLKALT = 3 (usually RESUME2)
相關PDF資料 |
PDF描述 |
|---|---|
| AD9923ABBCZRL | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| AD9925BBCZRL | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925 | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925BBCZ | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9927 | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9923ABBCZRL | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發布緊急采購，3分鐘左右您將得到回復。