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參數資料
| 型號： | AD9923ABBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 28/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZ |
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AD9923A
Rev. 0 | Page 28 of 88
Table 15. V-Sequence Registers
1
Register
HOLD
VMASK
Length
(Bits)
1
2
Range
On/off
0 to 3 mask mode
Description
Use in conjunction with VMASK. 1 = hold instead of FREEZE/RESUME.
Enables the masking of XV1 to XV13 outputs at the locations specified by
the FREEZE/RESUME registers.
0 = no mask.
1 = enable FREEZE1/RESUME1.
2 = enable FREEZE2/RESUME2.
3 = enable both FREEZE1/RESUME1 and FREEZE2/RESUME2.
HD line length in each V-sequence.
Start polarity for each XV1 to XV13 output.
HDLEN
XV1POL to
XV13POL
GROUPSEL
13
1
0 to 8191 pixels
High/low
12
1b for each XV output
Assigns each XV1 to XV13 output to either V-Pattern Group A or
V-Pattern Group B.
0 = assigns to VPATSELA.
1 = assigns to VPATSELB.
When high, all XV outputs combine Group A and Group B.
Selected V-pattern for Group A.
Selected V-pattern for Group B. If SPVTP_ENABLE = 1, VPATSELB is used
for second VTP inserted in SPVTP_ACTLINE.
Selects alternation repetition mode for Group A only.
0 = disable alternation, use VREPA_1 for all lines.
1 = 2-line. Alternate VREPA_1 and VREPA_2 (same as odd/even).
2 = 3-line. Alternate VREPA_1, VREPA_2, and VREPA_3.
3 = 4-line. Alternate VREPA_1, VREPA_2, VREPA_3, and VREPA_4.
Start position for the selected V-Pattern Group A.
Start position for the selected V-Pattern Group B. If SPVTP_ENABLE = 1,
VSTARTB is used for start position of VPATSELB in SPVTP_ACTLINE.
Length of selected V-Pattern Group A.
Length of selected V-Pattern Group B.
Number of repetitions for the V-Pattern Group B for odd lines.
If no alternation is required for Group B, set VREPB_ODD equal to
VREPB_EVEN.
Number of repetitions for the V-Pattern Group B for even lines.
If no alternation is required for Group B, set VREPB_EVEN equal to
VREPB_ODD.
Number of repetitions for the V-Pattern Group A for first lines (odd).
Number of repetitions for the V-Pattern Group A for second lines (even).
Number of repetitions for the V-Pattern Group A for third lines.
Number of repetitions for the V-Pattern Group A for fourth lines.
Pixel location where the XV outputs freeze or hold (see VMASK).
Pixel location where the XV outputs resume operation (see VMASK).
Pixel location where the XV outputs freeze or hold (see VMASK).
Pixel location where the XV outputs resume operation (see VMASK).
Active line for second VTP insertion.
When high, second VTP is inserted into SPVTP_ACTLINE.
TWO_GROUP
VPATSELA
VPATSELB
1
5
5
High/low
0 to 31 V-pattern number
0 to 31 V-pattern number
VPATA_MODE
VSTARTA
VSTARTB
2
13
13
0 to 3 repetition mode
0 to 8191 pixel location
0 to 8191 pixel location
VLENA
VLENB
VREPB_ODD
13
13
12
0 to 8191 pixels
0 to 8191 pixels
0 to 4095 repeats
VREPB_EVEN
12
0 to 4095 repeats
VREPA_1
VREPA_2
VREPA_3
VREPA_4
FREEZE1
RESUME1
FREEZE2
RESUME2
SPVTP_ACTLINE
SPVTP_ENABLE
1
See Table 11 and Table 12 for CLPOB, PBLK, and HBLK registers.
12
12
12
12
13
13
13
13
12
1
0 to 4095 repeats
0 to 4095 repeats
0 to 4095 repeats
0 to 4095 repeats
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 4095 line location
High/low
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相關代理商/技術參數 |
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| AD9923ABBCZRL | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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