- 您現在的位置：買賣IC網 > PDF目錄373971 > AD9929BBCZ (ANALOG DEVICES INC) CCD Signal Processor with Precision Timing Generator PDF資料下載
參數資料
| 型號： | AD9929BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-205-AB, CSBGA-64 |
| 文件頁數： | 21/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929BBCZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9929
Rev. A | Page 21 of 64
SDATA
SCK
SL
A
A
A
A
A
A
A
A
N
N
N
N
N
N
N
N
D
D
D
D
D
D
D
D
D
D
8 BIT ADDRESS
NUMBER OF 32 BIT
DATA WRITES (N)
DATA 1 [31:0]
D
D
D
D
D
D
D
DATA 2 [31:0]
D
D
D
D
DATA N [31:0]
DATA 1 [31:0]
NUMBER WRITES N [23:0]
ADDRESS [7:0]
DATA 2 [31:0]
DATA N [31:0]
1
1
12
NOTES
1. SL PULSES ARE IGNORED UNTIL THE LSB BIT OF THE LAST DATA N WORD IS CLOCKED IN.
2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.
0
Figure 11. System and Mode Register Writes
OPERATION OF VD SYNCHRONOUS
TYPE REGISTER WRITES BEGIN AT
THE NEXT VD FALLING EDGE.
0
VD
HD
CLI
PROGRAMMING VD SYNCHRONOUS
TYPE REGISTERS MUST BE
COMPLETED AT LEAST 4 CLI
CYCLES BEFORE THE FALLING
EDGE OF VD
Figure 12. VD Synchronous Type Register Writes
VD Synchronous and Asynchronous Register Operation
There are two types of control registers, VD synchronous and
VD asynchronous, as indicated in the address column of
Table 8. Register writes to synchronous and asynchronous
registers operate differently, as described in the following
sections. All writes to system Mode_A and Mode_B registers
occur asynchronously.
Asynchronous Register Operation
For VD asynchronous register writes, SDATA data is stored
directly into the serial register at the rising edge of SL. As a
result, register operation begins immediately after the rising
edge of SL.
VD Synchronous Register Operation
For VD synchronous registers, SDATA data is temporarily
stored in a buffer register at the rising edge of SL. This data is
held in the buffer register until the next falling edge of VD is
applied. Once the next falling edge of VD occurs, the buffered
SDATA data is loaded into the serial register, at which time the
register operation begins. See Figure 12.
All control registers at the following addresses are VD synchro-
nous type registers: Addresses 0x0A, 0x0B, 0x0C, 0x0D, and
0x0E. Also see Table 8, the Control Register Address Map.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9929 | CCD Signal Processor with Precision Timing Generator |
| AD9937 | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCP | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCPRL | TVPS00RF-25-35PB W/ PC CONTACT |
| AD9942 | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9929BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9937 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937BCPZ-24 | 制造商:Analog Devices 功能描述: |
| AD9937BCPZ-27 | 功能描述:IC CCD SIGNAL PROC/GEN 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
| AD9937BCPZRL-24 | 制造商:Analog Devices 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。