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參數資料
| 型號： | AD9929BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-205-AB, CSBGA-64 |
| 文件頁數： | 29/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929BBCZ |
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AD9929
HORIZONTAL CLAMPING AND BLANKING
The AD9929’s horizontal clamping and blanking pulses are
programmable to suit a variety of applications. As with the
vertical timing generation, individual sequences are defined for
each signal, which are then organized into multiple regions
during image readout. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout, in
order to accommodate different image transfer timing and high
speed line shifts.
Rev. A | Page 29 of 64
CONTROLLING CLPOB CLAMP PULSE TIMING
The AFE horizontal CLPOB pulse is generated based on the
12-bit gray code counter. Once the length of the 12-bit gray
code counter is set using the HDLEN register (Sys_Reg(12)),
the CLPTOG1 and CLPTOG2 registers (Sys_Reg(15 and 16))
can be used to place the CLPOB pulse location, as shown in
Figure 25. Table 19 lists all CLPOB registers that are used to
configure and control the placement and output of the
CLPOB pulse.
The length of the last HD line is set using the HDLASTLEN
register (Sys_Reg(1)). Figure 23 shows how no CLPOB pulse is
asserted when the last HD length set by HDLASTLEN is shorter
than the regular HD length set by HDLEN. Figure 24 shows
how no CLPOB pulse is applied when the last HD length set by
HDLASTLEN is longer than the regular HD length. Note that
the CLPOB pulse is applied in the last line only when
HDLASTLEN = HDLEN.
HD
CLPOB
LAST LINE
0
Figure 23. Last HD Shorter than Regular HD
HD
CLPOB
LAST LINE
0
Figure 24. Last HD Longer than Regular HD
Table 19. CLPOB Registers
Register
Name
CLPOB_CONT
CLPOB_MODE 1
Bit
Width
1
Register Type
Control (0x01)
Control (0x01)
Counter
Reference
–
–
Range
Description
CLPOB Control (0=CLPOB off, 1 =CLPOB On)
CLPOB CCD Region Control
(0 = Enable CLPENx Register Settings, 1 = Disable
CLPENx Register Settings)
CLPTOG1
12
Sys_Reg (15)
HD
0 to 4095 pixel
locations
0 to 4095 pixel
locations
CLPOB Toggle Position 1 (Gray Code Number)
CLPTOG2
12
Sys_Reg
(15 and 16)
Mode_Reg (2)
Mode_Reg (2)
Mode_Reg (2)
Mode_Reg (2)
Mode_Reg (2)
HD
CLPOB Toggle Position 2 (Gray Code Number)
CLPEN0
CLPEN1
CLPEN2
CLPEN3
CLPEN4
1
1
1
1
1
–
–
–
–
–
CLPOB Control for CCD Region 0
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPOB Control for CCD Region 1
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPOB Control for CCD Region 2
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPOB Control for CCD Region 3
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPOB Control for CCD Region 4
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9929BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9937 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937BCPZ-24 | 制造商:Analog Devices 功能描述: |
| AD9937BCPZ-27 | 功能描述:IC CCD SIGNAL PROC/GEN 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
| AD9937BCPZRL-24 | 制造商:Analog Devices 功能描述: |
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