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參數資料
| 型號： | AD9929BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-205-AB, CSBGA-64 |
| 文件頁數： | 39/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929BBCZ |
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AD9929
SPECIAL VERTICAL SWEEP MODE OPERATION
The AD9929 contains a special mode of vertical timing oper-
ation called sweep mode. This mode is used to generate a
continuous number of repetitive vertical pulses that span
multiple HD lines. One example of where this mode may be
needed is at the start of the CCD readout operation. At the end
of the image exposure, but before the image is transferred by the
sensor gate pulses, the vertical interline CCD registers should be
clean of all charge. This can be accomplished by quickly shifting
out any charge with a long series of pulses on the V1 to V4
outputs. This operation spans multiple HD line lengths.
Rev. A | Page 39 of 64
Normally the sequences are contained within one HD line
length but with the sweep mode enabled, the HD boundaries
will be ignored until the region is finished.
The special vertical sweep mode operation is only output in
CCD Region 0 and CCD Region 3 (see Figure 34), as shown in
Figure 37 and Figure 38. The SVREP_MODE register located at
Control Address 0x0A is used to enable and configure the
special sweep mode operation, as described in Table 25.
The maximum number of repeats in each region is 2048 while
operating in this mode using the SVREP0 and SVREP3
Mode_Reg(4) registers.
Table 25. Description of SVREP_MODE Register
SVREP_MODE
Description of Sweep Mode Operation
0
0
Normal Vertical Timing Operation in
all CCD Regions
0
1
Special Vertical Sweep Mode Timing
Output in CCD Region 0 Only
1
0
Special Vertical Sweep Mode Timing
Output in CCD Region 3 Only
1
1
Special Vertical Sweep Mode Timing
Output in CCD Region0 and CCD
Region 3
HD
XV1–XV4
0
Figure 35. Nonoverlapping Example while Operating in Normal Vertical Timing Operation SVREP_MODE = 0 and VTPREPx = 4
HD
XV1–XV4
NOT OUTPUT BECAUSE THE 8TH
REPETITION OVERLAPS WITH HD
0
Figure 36. Overlapping Example while Operating in Normal Vertical Timing Operation SVREP_MODE = 0 and VTPREPx = 8
SCP0
HD
XV1–XV4
CCD REGION 0
SCP1 = 3
0
1
2
0
0
Figure 37. Sweep Mode Timing Example with SVREP_MODE = 1 and SVREP0 = 28
HD
XV1–XV4
SCP3
SCP4 = 3
0
1
2
0
0
CCD REGION 3
Figure 38. Sweep Mode Timing Example with SVREP_MODE = 2 and SVREP3 = 28
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9929BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9937 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937BCPZ-24 | 制造商:Analog Devices 功能描述: |
| AD9937BCPZ-27 | 功能描述:IC CCD SIGNAL PROC/GEN 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
| AD9937BCPZRL-24 | 制造商:Analog Devices 功能描述: |
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