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參數(shù)資料
型號(hào): AD9929BBCZ
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: CCD Signal Processor with Precision Timing Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封裝: 9 X 9 MM, LEAD FREE, PLASTIC, MO-205-AB, CSBGA-64
文件頁數(shù): 43/64頁
文件大小: 558K
代理商: AD9929BBCZ
AD9929
V1 TO V4 AND SUBCK OUTPUT POLARITIES
As shown in Figure 41, the XV1 to XV4 and XSUBCK are
output signals from the AD9929 timing generator, whereas the
V1 to V1 and SUBCK are output signals from the AD9929
vertical driver. The V1 to V4 and SUBCK polarities are not the
same as the internal XV1 to XV4 and XSUBCK polarities
configured by the AD9929 registers. Table 28 through Table 32
describe the output polarities for these signals versus their input
levels. These tables must be referred to when determining the
register settings for the desired output levels. Figure 46 shows an
example of the V3 output.
Table 28. V1 Output Polarity
V-Driver Input
XV1
XVSG1
L
L
L
H
H
L
H
H
Table 29. V2 Output Polarity
V-Driver Input
XV2
L
H
Table 30. SUBCK Output Polarity
V-Driver Input
SUBCK Output
XSUBCK
L
VH2
H
VL
Rev. A | Page 43 of 64
V1 Output
VH1
VM1
VL
VL
V2 Output
VM2
VL
TIMING
GENERATOR
XV1
XV2
XV3
XV4
XVSG1
XSUBCK
V1
V2
V3
V4
SUBCK
XVSG2
V-DRIVER
LOGIC
V-DRIVER
BUFFERS
V-DRIVER
0
Figure 41. Internal XV1 to XV4 and XSUBCK Signals
Table 31. V3 Output Polarity
V-Driver Input
XV3
L
L
H
H
Table 32. V4 Output Polarity
V-Driver Input
XV4
L
H
V3 Output
VH1
VM1
VL
VL
XVSG2
L
H
L
H
V4 Output
VM2
VL
V1
V3
XVSG1
XVSG3
VH1
VM1
t
PMH
t
R2
t
PHM
t
F1
50%
50%
10%
90%
10%
90%
50%
50%
XV1
XV3
t
PLM1
t
R1
10%
90%
t
PML1
t
F2
10%
90%
VL
0
Figure 42. V1 and V3 Transmission Delays and Rise Times
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