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參數(shù)資料
型號： ADE7169ACPZF16
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： SPECIALTY ANALOG CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64
文件頁數(shù)： 112/140頁
文件大小： 1359K
代理商： ADE7169ACPZF16
ADE7169F16
Preliminary Technical Data
TEMPCAL
Table 107. RTC Configuration SFR (TIMECON, 0xA1)
Bit
Location
Mnemonic
7
MIDNIGHT
Rev. PrD | Page 112 of 140
0xF7
No
RTC temperature compensation
Bit
Default
Value
Description
Midnight Flag
This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by
the user to indicate that the midnight event has been serviced. In twenty-
four hour mode, the midnight flag is raised once a day at midnight.
Twenty-four hour mode
0
256 Hour mode. The HOUR register will roll over from 255 to 0.
1
24 Hour mode. The HOUR register will roll over from 23 to 0.
Note: This bit is retained during a watchdog reset or an external reset. It is
reset after a power on reset (POR).
Interval Timer Timebase Selection
ITS[1:0]
Timebase
0
0
1/128 second
0
1
Second
1
0
Minute
1
1
Hour
Interval Timer One-Time Alarm
0
The ALARM flag will be set after INTVAL counts and then another
interval count will start.
1
The ALARM flag will be set after one time interval.
Interval Timer Alarm Flag
This bit is set when the configured time interval has elapsed. It can be
cleared by the user to indicate that the alarm event has been serviced.
0
6
TFH
0
5-4
ITS[1:0]
0
3
SIT
0
2
ALARM
0
Interval Timer Enable
0
The interval timer is disabled. The 8-bit interval timer counter is
reset.
1
Set this bit to enable the interval timer. The RTCEN bit must also
be set to enable the interval timer.
RTC Enable. Also Temperature, Battery and Supply ADC Background
Strobe Enable
0
The RTC and interval timer are disabled and the RTC registers are
cleared. When this bit is clear, the background ADC strobe timer
is disabled.
1
The RTC is enabled. The background ADC strobe timer is enabled.
Note: This bit is retained during a watchdog reset or an external reset. It is
reset after a power on reset (POR).
1
ITEN
0
0
RTCEN
1
Table 108. Hundredths of a Second Counter SFR (HTHSEC, 0xA2)
Bit
Location
Mnemonic
7-0
HTHSEC
Bit
Default
Value
Description
This counter updates every 1/128 second, referenced from the calibrated
32kHz clock. It overflows from 127 to 00, incrementing the seconds
counter, SEC.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
0
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