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參數資料
| 型號： | ADE7169ACPZF16 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64 |
| 文件頁數： | 88/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPZF16 |
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Preliminary Technical Data
ADE7169F16
LCD DRIVER
The LCD module is capable of directly driving an LCD panel of
24 x 4 segments without compromising any ADE7169F16
functionalities. Using shared pins, the driver can accommodate
an LCD with up to 26 x 4 segments. It is capable of driving
LCDs with 2x, 3x and 4x multiplexing. LCD waveform voltages
generated through internal charge pump circuitry support up to
5V LCDs. An external resistor ladder for LCD waveform
voltage generation is also supported.
Rev. PrD | Page 88 of 140
The ADE7169F16 has an embedded LCD control circuit, LCD
driver and power supply circuit. The LCD module is functional
in all Operating modes.
Table 70. LCD Driver SFRs
SFR
address
(hex)
LCD SFR REGISTER LIST
There are six LCD control registers that configure the driver for
the specific type of LCD in the end system and set up the user
display preferences. The LCD Configuration SFR (LCDCON,
0x95), LCD Configuration X SFR (LCDCONX, 0x9C) and LCD
Configuration Y SFR (LCDCONY, 0xB1) SFRs contains general
LCD driver configuration information including the LCD
enable and reset, as well as method of LCD voltage generation
and the multiplex level. The LCD Clock SFR (LCDCLK, 0x96)
configures timing settings for LCD frame rate and blink rate.
LCD pins are configured for LCD functionality in the LCD
Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment
Enable 2 SFR (LCDSEGE2, 0xED).
R/W
Name
Description
0x95
R/W
LCDCON
LCD Configuration SFR
0x96
R/W
LCDCLK
LCD Clock
0x97
R/W
LCDSEGE
LCD Segment Enable
0x9C
R/W
LCDCONX
LCD Configuration X
0xAC
R/W
LCDPTR
LCD Pointer
0xAE
R/W
LCDDAT
LCD Data
0xB1
R/W
LCDCONY
LCD Configuration Y
0xED
R/W
LCDSEGE2
LCD Segment Enable 2
Table 71. LCD Configuration SFR (LCDCON, 0x95)
Bit
Location
Mnemonic
7
LCDEN
Bit
Default
Value
Description
0
LCD enable.
If this bit is set, the LCD driver is enabled.
LCD data registers are reset to zero.
If this bit is set, the LCD data registers will be reset to zero.
Blink Mode enable bit.
If this bit is set, blink mode is enabled. The blink mode is configured by the
BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96)
Force LCD off when in PSM2 (Sleep mode).
0 The LCD is disabled or enabled in PSM2 by LCDEN bit.
1 The LCD is disabled in PSM2 regarless of LCDEN setting.
LCD clock selection
f
LCDCLK
0
2048Hz
1
128Hz
Bias Mode
0
1/2
1
1/3
LCD Multiplex level
6
LCDRST
0
5
BLINKEN
0
4
LCDPSM2
0
3
CLKSEL
0
2
BIAS
0
1-0
LMUX[1:0]
0
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