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參數(shù)資料
型號： ADE7169ACPZF16
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： SPECIALTY ANALOG CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64
文件頁數(shù)： 24/140頁
文件大小： 1359K
代理商： ADE7169ACPZF16
ADE7169F16
Preliminary Technical Data
Rev. PrD | Page 24 of 140
Set when V
SW
switches from V
DD
to V
BAT.
V
DCIN
Monitor interrupt flag.
Set when V
DCIN
falls below 1.2V.
0
0xF8
FVDC
0
Table 14. Battery Switchover Configuration SFR (BATPR, 0xF5)
Bit
Location
Mnemonic
7-2
Reserved
1-0
BATPRG [1:0]
Bit
Default
Value
00
00
Description
These bits must be kept to 0 for proper operation
Control bits for Battery Switchover.
BATPRG [1:0]
0
0
1
Function
Battery Swichover Enabled on Low V
DD
Battery Swichover Enabled on Low V
DD
and Low V
DCIN
Battery Switchover Disabled
0
1
X
Table 15. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit
Location
Mnemonic
7
RXFLAG
6
VSWSOURCE
Bit
Default
Value
0
1
Description
If set, indicates that a RX Edge event triggered wakeup from PSM2
Indicates the power supply that is connected internally to V
SW
.
0 V
SW
=V
BAT
1 V
SW
=V
DD
If set, indicates that VDD power supply is ok for operation
5
VDD_OK
1
4
PLL_FLT
0
If set, indicates that PLL is not locked
3
REF_BAT_EN
0
If set, Internal voltage reference enabled in PSM2 mode. This bit should be set if LCD On in
PSM2 mode.
This bit should be kept to zero
Controls the function of the P1.0/RX pin.
RXPROG [1:0]
Function
0
0
GPIO
0
1
RX with wakeup disabled
1
1
RX with wakeup enabled
2
1-0
Reserved
RXPROG[1:0]
0
00
Table 16. Power Management Interrupt Enable SFR (IPSME, 0xEC)
Bit
Location
Mnemonic
Value
7
EPSR
0
6
ADEIAUTCLR
0
5
ESAG
0
4
RESERVED
0
3
EVSW
0
2
EBAT
0
1
EBSO
0
0
EVDCIN
0
Table 17. Scratch Pad 1 SFR (SCRATCH1, 0xFB)
Bit
Location
Mnemonic
Value
7-0
SCRATCH1
0
Bit
Default
Description
Enables a PSM interrupt when the Power Supply Restored flag is set.
If set, the ADE interrupt status registers MIRQSTH/M/L registers will be read with reset.
Enables a PSM interrupt when the voltage sag flag (FSAG) is set.
This bit must be kept cleared for proper operation
Enables a PSM interrupt when the V
SW
monitor flag (FVSW) is set.
Enables a PSM interrupt when the V
BAT
monitor flag (FBAT) is set.
Enables a PSM interrupt when the Battery Switchover flag (FBSO) is set.
Enables a PSM interrupt when the V
DCIN
monitor flag (FVDCIN) is set.
Bit
Default
Description
Value can be written/read in this register. This value will be maintained in all the power
saving modes of the ADE7169F16
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