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參數資料
| 型號： | ADE7169ACPZF16 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64 |
| 文件頁數： | 123/140頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | ADE7169ACPZF16 |
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Preliminary Technical Data
ADE7169F16
SERIAL PERIPHERAL INTERFACE
INTERFACE (SPI)
The ADE7169F16 integrates a complete hardware serial
peripheral interface on-chip. The SPI interface is full duplex so
that eight bits of data are synchronously transmitted and
received simultaneously. This SPI implementation is double
buffered. This allows the user to read the last byte of received
data while a new byte is shifted in. The next byte to be
transmitted can be loaded while the current byte is shifted out.
Rev. PrD | Page 123 of 140
The SPI port can be configured for Master or Slave operation.
The physical interface to the SPI is done via MISO (P0.3),
MOSI (P0.2), SCLK (P0.4) and
SS
(P0.5) pins, while the
firmware interface is done via the
SPI Configuration Register SFR
(SPIMOD1, 0xE8)
,
SPI Configuration Register SFR (SPIMOD2,
0xE9)
,
SPI Interrupt Status Register SFR (SPISTAT, 0xEA)
,
SPI/I2C
Transmit Buffer SFR (SPI2CTx, 0x9A)
and
SPI Receive Buffer SFR
(SPI2CRx, 0x9B)
.
Note that the SPI pins are shared with the I
2
C pins. Therefore,
the user can enable only one interface at a time. The SCPS bit in
the CFG SFR selects which peripheral is active.
SPI SFR REGISTER LIST
SFR Address
Name
R/W
Length
Default
Value
0
0x10
0
0
Description
0x9A
0x9B
0xE8
0xE9
0xEA
SPI2CTx
SPI2CRx
SPIMOD1
SPIMOD2
SPI2CSTAT
W
R
R/W
R/W
R/W
8
8
8
8
8
SPI Data out register
SPI Data in register
SPI configuration register
SPI configuration register
SPI/I2C Interrupt Status register
Table 121: SPI SFR register list
Table 122. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)
Bit
Location
Mnemonic
7-0
SPI2CTx
Bit
Default
Value
Description
0
SPI or I2C transmit buffer
When SPI2CTx SFR is written, its content is transfered to the transmit FIFO input.
When a write is requested, the FIFO output is sent on the SPI or I2C bus.
Table 123. SPI Receive Buffer SFR (SPI2CRx, 0x9B)
Bit
Location
Mnemonic
7-0
SPI2CRx
Bit
Default
Value
Description
0
SPI or I2C receive buffer
When SPI2CRx SFR is read, one byte from the Receive FIFO output is transfered to
SPI2CRx SFR. A new data from the SPI or I2C bus is written to the FIFO input.
Table 124. SPI Configuration Register SFR (SPIMOD1, 0xE8)
Bit
Location
Addr.
Name
7-5
0xEF –
0xEE
5
0xED
INTMOD
Bit
Bit
Default
Value
Description
Reserved
0
Reserved
0
SPI Interrupt mode
0: SPI Interrupt set when SPI Rx buffer full
1: SPI interrupt set when SPI Tx buffer empty
Master Mode: SS output control. See Figure 82.
0
The SS is held low while this bit is clear. This allows manual chip select
control using the SS pin.
Single Byte Read or Write: The SS will go low during a single byte
transmission and then return high.
Continuous Transfer: The SS will go low during the duration of the multi-
byte continuous transfer and then return high.
Slave Mode: SS input enable
0xEC
4
AUTO_SS
1
1
3
0xEB
SSE
0
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