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參數(shù)資料
型號： ADE7169ACPZF16
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： SPECIALTY ANALOG CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64
文件頁數(shù)： 40/140頁
文件大小： 1359K
代理商： ADE7169ACPZF16
ADE7169F16
Preliminary Technical Data
Rev. PrD | Page 40 of 140
Location
Mnemonic
Reserved
SEL_I_CH[1:0]
Value
7 – 6
5 - 4
0
0
These bits should be kept cleared for proper operation
These bits define the current channel used for energy measurements
[1:0]
00
Current channel automatically selected by the tampering condition
01 Current channel connected to I
A
10 Current channel connected to I
B
11 Current channel automatically selected by the tampering condition
Logic one short voltage channel to ground
Logic one short Current channels to ground
3
2
1 - 0
V_CH_SHORT
I_CH_SHORT
Reserved
0
0
Table 35. Interrupt Status Register 1 SFR (MIRQSTL, 0xDC)
Bit
Location
7
ADEIRQFLAG
Interrupt Flag
Description
This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt
are set. This bit is automatically cleared when all of the enabled ADE status flags are
cleared.
Reserved.
Logic one indicates that the Fault mode has changed according to the configuration of
the ACCMODE register
Logic one indicates that the reactive power sign changed according to the configuration
of ACCMODE register
Logic one indicates that the active power sign changed according to the configuration of
ACCMODE register
Logic one indicates that an interrupt was caused by apparent power no-load detected.
This interrupt is also used to reflect the part entering the IRMS No load mode.
Logic one indicates that an interrupt was caused by reactive power no-load detected.
Logic one indicates that an interrupt was caused by active power no-load detected.
6
5
Reserved
FAULTSIGN
4
VARSIGN
3
APSIGN
2
VANOLOAD
1
0
RNOLOAD
APNOLOAD
Table 36. Interrupt Status Register 2 SFR (MIRQSTM, 0xDD)
Bit
Location
7
CF2
Interrupt Flag
Description
Logic one indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse
output is not enabled by clearing bit 2 of MODE1 register.
Logic one indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse
output is not enabled by clearing bit 1 of MODE1 register.
Logic one indicates that the VAHR register has overflowded
Logic one indicates that the VARHR register has overflowded
Logic one indicates that the WATTHR register has overflowded
Logic one indicates that the VAHR register is half full
Logic one indicates that the VARHR register is half full
Logic one indicates that the WATTHR register is half full
6
CF1
5
4
3
2
1
0
VAEOF
REOF
AEOF
VAEHF
REHF
AEHF
Table 37. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE)
Bit
Location
7
RESET
6
-
5
WFSM
4
PKI
3
PKV
Interrupt Flag
Description
Indicates the end of a reset (for both sofware or hardware reset).
Reserved
Logic one indicates that new data is present in the Waveform Registers
Logic one indicates that current channel has exceeded the IPKLVL value
Logic one indicates that voltage channel has exceeded the VPKLVL value.
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