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參數(shù)資料
型號： ADE7169ACPZF16
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： SPECIALTY ANALOG CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64
文件頁數(shù)： 137/140頁
文件大小： 1359K
代理商： ADE7169ACPZF16
Preliminary Technical Data
ADE7169F16
Rev. PrD | Page 137 of 140
P0.5
MISO SPI Data line
Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set
the SPIEN bit in the SPI Configuration Register SFR
(SPIMOD2, 0xE9)
Set the I2CEN bit in the I2CMOD SFR or the SPIEN bit in the
SPI Configuration Register SFR (SPIMOD2, 0xE9) to enable
the I
2
C or SPI interface
Set the CNT0 bit in the Timer/Counter 0 and 1 Mode SFR
(TMOD, 0x89) to enable T0 as an external event counter
Set the SS_EN bit in the SPI Configuration Register SFR
(SPIMOD1, 0xE8)
SCLK serial clock for I
2
C or SPI
P0.6
T0 Timer0 input
SS SPI slave select input for SPI in slave mode
SS SPI slave select output for SPI in master
mode
Set the SPIMS_b bit in the SPI Configuration Register SFR
(SPIMOD2, 0xE9)
P0.7
T1 Timer 1 input
Set the CNT1 bit in the Timer/Counter 0 and 1 Mode SFR
(TMOD, 0x89) to enable T1 as an external event counter
Table 142. Port 1 Alternate Functions
Pin
No.
RxD Receiver Data Input for UART
P1.0
Alternate Function
Alternate Function Enable
Set the REN bit in the SCON SFR Bit Description SFR (SCON,
0x98).
Set RXPROG[1:0]=11 in the Peripheral Configuration SFR
(PERIPH, 0xF4)
Set FP25EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP24EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set EXEN2 in the Timer/Counter 2 Control SFR (T2CON, 0xC8)
Set FP23EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set the CNT2 bit in the Timer/Counter 2 Control SFR (T2CON,
0xC8) to enable T2 as an external event counter
Set FP22EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP21EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP20EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
RX Edge wakeup from PSM2 operating mode
P1.1
P1.2
P1.3
TxD Transmitter Data Output for UART
FP25 LCD Segment Pin
FP24 LCD Segment Pin
T2EX Timer 2 control input
FP23 LCD Segment Pin
T2 Timer 2 input
P1.4
P1.5
P1.6
P1.7
FP22 LCD Segment Pin
FP21 LCD Segment Pin
FP20 LCD Segment Pin
Table 143. Port 2 Alternate Functions
Pin
No.
P2.0
FP18 LCD Segment Pin
Alternate Function
Alternate Function Enable
Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
Enabled by default.
P2.1
FP17 LCD Segment Pin
P2.2
FP16 LCD Segment Pin
P2.3
SDEN Serial Download pin sampled on reset.
P2.3 is an output only.
PORT 0
Port 0 is controlled directly through the bit-addressable Port 0 SFR (80H). The weak internal pull-ups for Port 0 are configured through
the Port 0 Weak pull-up enable SFR (PINMAP0, 0xB2); they are enabled by default. Disable the weak internal pull-up by writing a one to
P0CFG..x.
Port 0 pins also have various secondary functions as described in Table 141. The alternate functions of Port 0 pins can be activated only if
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