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參數資料
| 型號： | ADE7169ACPZF16 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64 |
| 文件頁數： | 39/140頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | ADE7169ACPZF16 |
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Preliminary Technical Data
ADE7169F16
Rev. PrD | Page 39 of 140
Location
7
Mnemonic
ICHANNEL
Value
0
This bit indicate the current channel used to measure energy in anti-
tampering mode.
0 – Channel A
1 – Channel B
Configuration bit to select event that will trigger a Fault interrupt
0 – FAULT interrupt occurs when part enters Fault Mode
1 – FAULT interrupt occurs when part enters Normal Mode
Configuration bit to select event that will trigger an reactive power sign
interrupt
0 – VARSIGN interrupt occurs when reactive power changes from positive
to negative
1 - VARSIGN interrupt occurs when reactive power changes from negative
to positive
Configuration bit to select event that will trigger an active power sign
interrupt
0 – APSIGN interrupt occurs when active power changes from positive to
negative
1 - APSIGN interrupt occurs when active power changes from negative to
positive
Logic one enables absolute value accumulation of Reactive power in
energy register and pulse output
Logic one enables reactive power accumulation depending on the sign of
the active power:
If Active Power is positive, VAR is accumulated as it is;
If Active Power is negative, the sign of the VAR is reversed for the
accumulation.
This accumulation mode affects both the VAR registers and the VARCF
output.
Logic one enables positive only accumulation of Active power in energy
register and pulse output
Logic one enables absolute value accumulation of Active power in energy
register and pulse output
6
FAULTSIGN
0
5
VARSIGN
0
4
APSIGN
0
3
ABSVARM
0
2
SAVARM
0
1
POAM
0
0
ABSAM
0
Table 33. GAIN register (0x1B)
Bit
Location
7 - 5
Bit
Mnemonic
PGA2[2:0]
Default
Value
Description
0
These bits define the voltage channel input gain
[2:0]
000
Gain = 1
001
Gain = 2
010
Gain = 4
011
Gain = 8
100
Gain = 16
Reserved
These bits define the current channel input gain
[2:0]
000
Gain = 1
001
Gain = 2
010
Gain = 4
011
Gain = 8
100
Gain = 16
4 - 3
2 - 0
Reserved
PGA1[2:0]
0
0
Table 34. CALMODE register (0x3D)
Bit
Bit
Default
Description
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