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參數資料
| 型號： | ADE7169ACPZF16 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64 |
| 文件頁數： | 72/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPZF16 |
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ADE7169F16
Preliminary Technical Data
Table 54. Program Control SFR (PCON, 0x87)
Bit Location
Default
7
0
6-0
0
Table 55. Data Pointer Low SFR (DPL, 0x82)
Bits
Default
Description
7-0
0
Contain the low byte of the data pointer
Table 56. Data Pointer High SFR (DPH, 0x83)
Bits
Default
Description
7-0
0
Contain the high byte of the data pointer
Rev. PrD | Page 72 of 140
Description
Double baud rate control
Reserved, should be left cleared
Table 57. Stack Pointer SFR (SP, 0x81)
Bits
Default
Description
7-0
7
Contain the 8 LSB of the pointer for the stack
Table 58. Configuration SFR (CFG, 0xAF)
Bit
Location
7
Reserved.. This bit should be left set for proper operation.
Enhanced UART enable bit
0
1
Bit Mnemonic
Description
Standard 8052 UART without enhanced error checking features
Enhanced UART with enhanced error checking—see the UART additional features
section.
Synchronous communication selection bit
0
I2C port is selected for control of the shared I2C/SPI pins and SFRs
1
SPI port is selected for control of the shared I2C/SPI pins and SFRs
38kHz modulation enable bit
0
38kHz modulation is disabled.
1
38kHz modulation is enabled on the pins selected by the MOD38[7:0] bits in the
EP_CFG SFR.
6
EXTEN
5
SCPS
4
MOD38EN
3-2
1-0
Reserved
XREN[1:0]
XREN[1] OR
XREN[0] =1
XREN[1] AND
XREN[0] =0
Enable MOVX instruction to use 256 bytes of Extended RAM.
Disable MOVX instruction
BASIC 8052 REGISTERS
Program Counter (PC):
The Program Counter holds the two
byte address of the next instruction to be fetched. The PC is
initialized with 0x00 at Reset and is incremented after each
instruction is performed. Note that the amount that is added to
the PC depends on the number of bytes in the instruction, so
the increment can range from one to three bytes. The program
counter is not directly accessible to the user but can be directly
modified by CALL and JMP instructions that change which
part of the program is active.
Instruction Register (IR):
The Instruction Register holds the
opcode of the instruction being executed. The opcode is the
binary code that results from assembling an instruction. This
register is not directly accessible to the user.
Register Banks:
There are four banks containing 8 byte-wide
registers each, for a total of 32 bytes of registers. These registers
are convenient for temporary storage of mathematical operands.
An instruction involving the accumulator and a register can be
executed in 1 clock cycle as opposed to 2 clock cycles to
perform an instruction involving the accumulator and a literal
or a byte of general purpose RAM. The register banks are
located in the first 32 bytes of RAM.
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