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參數資料
| 型號： | ADE7169ACPZF16 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64 |
| 文件頁數： | 85/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPZF16 |
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Preliminary Technical Data
ADE7169F16
Table 67. Interrupt Flags
Interrupt Source
Rev. PrD | Page 85 of 140
Flags
Bit
Address
IE0
TF0
IE1
TF1
TI
RI
TF2
EXF2
Details
IE0
TF0
IE1
TF1
RI + TI
TCON.1
TCON.5
TCON.3
TCON.7
SCON.1
SCON.0
T2CON.7
T2CON.6
External Interrupt 0
Timer 0
External Interrupt 1
Timer 1
Transmit Interrupt
Receive Interrupt
Timer 2 overflow flag
Timer 2 external flag
The Temperature ADC interrupt does not have an interrupt flag associated with it.
TF2 + EXF2
ITEMP (Temperature
ADC)
IPSM (Power
Supply)
IADE (Energy
Measurement DSP)
-
IPSMF.6
FPSM
PSM interrupt flag
MIRQSTL.7
Read MIRQSTH, MIRQSTM, MIRQSTL. If the AUTOCLR bit in the IPSME SFR is set, each
of these bytes will be reset after they are read. This is done on a per byte basis.
Reading MIRQSTH reads and clears only MIRQSTH.
Table 68. Status Flags
Interrupt Source
Flags
Bit
Address
WDS
Details
ITEMP (Temperature ADC)
ISPI/I2CI
-
The Temperature ADC interrupt does not have an status flag associated with it.
SPI Interrupt Status register
I
2
C Interrupt Status register
RTC Midnight flag
RTC Alarm flag
Watchdog Timeout flag
SPI2CSTAT
SPI2CSTAT
TIMECON.7
TIMECON.2
WDCON.2
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
A functional block diagram of the interrupt system is shown in
Figure 62. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external
wakeup event
occurs to wake the ADE7169F16
from PSM2, a pending external interrupt will be generated.
When the EX0 or EX1 bits are set in the Interrupt Enable SFR
(IE, 0xA8) to enable external interrupts, the program counter
will be loaded with the IE0 or IE1 interrupt vector. The IE0 and
IE1 interrupt flags in the TCON register will not be affected by
events that occur when the 8052 MCU core is shut down during
PSM2 — see the Power Supply Monitor Interrupt (PSM)
section.
The RTC, temperature ADC and I2C/SPI interrupts are latched
such that pending interrupts cannot be cleared without entering
their respective interrupt service routines. Clearing the RTC
Midnight and Alarm flags will not clear a pending RTC
interrupt. Similarly, clearing the I2C/SPI status bits in the SPI
Interrupt Status Register SFR (SPISTAT, 0xEA) will not cancel a
pending I2C/SPI interrupt. These interrupts will remain
pending until the RTC or I2C/SPI interrupt vectors are enabled.
Their respective interrupt service routines will be entered
shortly thereafter.
Figure 62 shows how the interrupts are cleared when the
interrupt service routines are entered. Some interrupts with
multiple interrupt sources are not automatically cleared,
specifically the PSM, ADE, UART and Timer 2 interrupt
vectors. Note that the INT0 and INT1 interrupts are only
cleared if the external interrupt is configured to be triggered by
a falling edge, by setting IT0 in the Timer/Counter 0 and 1
Control SFR (TCON, 0x88). If INT0 or INT1 is configured to
interrupt on a low level, the interrupt service routine will be
reentered until the respective pin goes high.
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