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參數資料
| 型號： | ISP1183BS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Low-power Universal Serial Bus interface device with DMA |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC32 |
| 封裝： | 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32 |
| 文件頁數： | 12/62頁 |
| 文件大小： | 295K |
| 代理商： | ISP1183BS |
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Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
12 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
A hardware reset disables all USB endpoints and clears all Endpoint Configuration
registers (ECRs), except for the control endpoint that is fixed and always enabled.
Section 10.3
explains how to (re)initialize endpoints.
9.
Interrupts
Figure 8
shows the interrupt logic of the ISP1183. Each of the indicated USB events
is logged in a status bit of the Interrupt register. Corresponding bits in the Interrupt
Enable register determine whether an event will generate an interrupt.
Interrupts can be masked globally using bit INTENA of the Mode register (see
Table 18
).
The signaling mode of output INT is controlled by bit INTLVL of the Hardware
Configuration register (see
Table 20
). Default settings after reset is level mode. When
pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination
of all interrupt bits changes from logic 0 to logic 1.
Bits SUSPND, RESET, RESUME, SP_EOT, EOT and SOF are cleared when the
Interrupt register is read. The endpoint bits (EP0OUT to EP14) are cleared when the
associated Endpoint Status register is read.
Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the
current bus status when reading the Interrupt register.
Fig 8.
Interrupt logic.
004aaa255
.
.
.
IERST
i
IESUSP
IERESM
IESOF
IEP14
...
IEP0IN
IEP0OUT
device mode
register
INTENA
INTLVL
hardware configuration
register
PULSE
GENERATOR
INT
1
0
.
.
.
.
.
.
.
.
interrupt register
RESET
SUSPND
RESUME
SOF
EP14
...
EP0IN
EP0OUT
.
.
.
.
.
.
.
.
.
.
RESET
reset interrupt source
suspend interrupt source
EPn interrupt source
(clear EPn interrupt; reading EPn
status register will set this signal)
(clear SUSPEND interrupt; reading
interrupt register will set this signal)
(clear RESET interrupt; reading
interrupt register will set this signal)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1183BS,118 | 功能描述:USB 接口集成電路 FULL-SPD USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1183BS,151 | 功能描述:USB 接口集成電路 FULL-SPD USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1183BS,157 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1183BSFA | 功能描述:IC USB HOST CTRL LOW-SPD 32HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1183BS-S | 功能描述:USB 接口集成電路 FULL-SPD USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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