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參數資料
| 型號： | MPC823UM_REV1_16-CPM7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 10 AMP SUBMINIATURE POWER RELAY |
| 中文描述： | 通信處理器模塊 |
| 文件頁數： | 19/74頁 |
| 文件大小： | 234K |
| 代理商： | MPC823UM_REV1_16-CPM7 |
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Communication Processor Module
MOTOROLA
MPC823 REFERENCE MANUAL
16-397
S
C
1
P
E—Empty
0 = The data buffer associated with this RX buffer descriptor is filled with received data
or data reception is aborted due to an error condition. The core is free to examine
or write to any fields of this RX buffer descriptor. The communication processor
module does not use this buffer descriptor as long as the E bit is zero.
1 = The data buffer associated with this buffer descriptor is empty or reception is
currently in progress. This RX buffer descriptor and its associated receive buffer
are owned by the communication processor module. Once the E bit is set, the core
must not write any fields of this RX buffer descriptor.
Bits 1, 4–5, 8–9, 13, and 15—Reserved
These bits are reserved and must be set to 0.
W—Wrap (Final Buffer Descriptor in Table)
0 = This is not the last buffer descriptor in the RX buffer descriptor table.
1 = This is the last buffer descriptor in the RX buffer descriptor table. After this buffer
is used, the communication processor module receives incoming data into the first
buffer descriptor that RBASE points to in the table. The number of RX buffer
descriptors in this table is programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
I—Interrupt
0 = No interrupt is generated after this buffer is filled.
1 = The RX bit in the event register is set when this buffer is completely filled by the
communication processor module, indicating the need for the core to process the
buffer. The RX bit can cause an interrupt if it is enabled.
CM—Continuous Mode
0 = Normal operation.
1 = The E bit is not cleared by the communication processor module after this buffer
descriptor is closed, thus allowing the associated data buffer to be automatically
overwritten next time the communication processor module accesses this buffer
descriptor. However, the E bit is cleared if an error occurs during reception,
regardless of how the CM bit is set.
ID—Buffer Closed on Reception of Idles
This bit indicates that the buffer has closed because a programmable number of consecutive
idle sequences have been received. The communication processor module writes this bit
after the received data is in the associated data buffer.
BR—Buffer Closed on Reception of Break
This bit indicates that the buffer has closed because a break sequence has been received.
The communication processor module writes this bit after the received data is in the
associated data buffer.
0 = No break sequence is received.
1 = A break sequence is received and the buffer closes.
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