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參數資料
| 型號： | MPC823UM_REV1_16-CPM7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 10 AMP SUBMINIATURE POWER RELAY |
| 中文描述： | 通信處理器模塊 |
| 文件頁數： | 55/74頁 |
| 文件大小： | 234K |
| 代理商： | MPC823UM_REV1_16-CPM7 |
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Communication Processor Module
MOTOROLA
MPC823 REFERENCE MANUAL
16-433
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C
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16.12.3 The SPI Transmission and Reception Process
When the serial peripheral interface is in master mode, it transmits a message to the
peripheral or slave, which sends back an immediate reply. When the MPC823 has more
than one slave, it can use the general-purpose parallel I/O pins to selectively enable different
slaves. To start the data exchange process, the core writes the data to be transmitted into
a data buffer, configures a transmit (TX) buffer descriptor with its R bit set, and configures
one or more receive (RX) buffer descriptors. The core then sets the STR bit in the SPCOM
register to start transmitting data, which starts when the SDMA channel loads the transmit
FIFO with data.
The serial peripheral interface then generates programmable clock pulses on the SPICLK
pin for each character and shifts the data out on the SPIMOSI pin. At the same time, the
serial peripheral interface shifts received data in from the SPIMISO pin. This received data
is written into a receive buffer using the next available RX buffer descriptor. The serial
peripheral interface continues transmitting and receiving characters until the transmit buffer
has been completely transmitted or an error has occurred. The communication processor
module then clears the R and E bits in the TX and RX buffer descriptors and may issue a
maskable interrupt to the CPM interrupt controller.
When multiple TX buffer descriptors are ready to be transmitted, the L bit in the TX buffer
descriptor determines whether or not the serial peripheral interface must continue
transmitting without waiting for the STR bit to be set again. If the L bit is cleared, the data
from the next TX buffer descriptor begins transmitting after data from the first TX buffer
descriptor is transmitted. If the L bit is set, transmission stops after data from this TX buffer
descriptor has finished transmitting. In addition, the current RX buffer descriptor that is used
to receive data is closed after transmission stops, even if the receive buffer is not full. This
means that you do not need to provide receive buffers that are the same length as the
transmit buffers. If the serial peripheral interface is the only master in a system, then the
SPISEL pin can be used as a general-purpose I/O, and the internal SPISEL signal to the
serial peripheral interface is always forced internally inactive, thus eliminating the possibility
of a multimaster error.
When the serial peripheral interface is in slave mode, it receives messages from an SPI
master and sends back an immediate reply. The SPISEL pin must be asserted before
receive clocks are recognized and once SPISEL is asserted, the SPICLK pin becomes an
input from the master to the slave. SPICLK can be any frequency from the DC to the
BRGCLK/2, which is 12.5MHz for a 25MHz system.
Before the data is exchanged, the core writes the data to be transmitted into a data buffer,
configures a TX buffer descriptor with its R bit set, and configures one or more RX buffer
descriptors. The core then sets the STR bit in the SPCOM register to enable the serial
peripheral interface so it will prepare the data for transmission and wait for the SPISEL pin
to be asserted. Data is shifted out from the slave on the SPIMISO pin and shifted in through
the SPIMOSI pin. A maskable interrupt is issued when a full buffer finishes receiving and
transmitting or after an error occurs. Using the next RX buffer descriptor in the ring, the serial
peripheral interface continues reception until it runs out of receive buffers or the SPISEL pin
is negated.
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