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參數(shù)資料
| 型號： | MPC823UM_REV1_16-CPM7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 10 AMP SUBMINIATURE POWER RELAY |
| 中文描述： | 通信處理器模塊 |
| 文件頁數(shù)： | 22/74頁 |
| 文件大小： | 234K |
| 代理商： | MPC823UM_REV1_16-CPM7 |
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Communication Processor Module
16-400
MPC823 REFERENCE MANUAL
MOTOROLA
S
C
1
P
16.11.6.12 SMCx UART TRANSMIT BUFFER DESCRIPTOR.
Data is sent to the
communication processor module for transmission on an SMCx channel by arranging it in
buffers referenced by the channel’s transmit (TX) buffer descriptor ring. Using the buffer
descriptors, the communication processor module confirms transmission or indicates error
conditions so that the processor knows the buffers have been serviced.
R—Ready
0 = The data buffer associated with this buffer descriptor is not ready for transmission,
but you are free to manipulate this buffer descriptor or its associated data buffer.
The communication processor module clears this bit after the buffer has been
transmitted or an error condition is encountered.
1 = The data buffer, which you prepare for transmission, is not transmitted yet or is
currently being transmitted. You cannot write any fields of this buffer descriptor
once this bit is set.
Bits 1, 4–5, and 8–15—Reserved
These bits are reserved and must be set to 0.
W—Wrap (Final Buffer Descriptor in Table)
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is
used, the communication processor module receives incoming data into the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table is programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
I—Interrupt
0 = No interrupt is generated after this buffer is serviced.
1 = The TX bit in the SMCE–UART register is set when this buffer is serviced.
Transmission can cause an interrupt if it is enabled.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OFFSET + 0
R
RES
W
I
RESERVED
CM
P
RESERVED
OFFSET + 2
DATA LENGTH
OFFSET + 4
TX DATA BUFFER POINTER
OFFSET + 6
NOTE:
You are only responsible for initializing the items in bold.
Note:
The communication processor module sets all the status bits in this buffer
descriptor, but you must clear them before submitting the buffer descriptor to the
communication processor module.
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