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參數資料
型號: MPC823UM_REV1_16-CPM7
廠商: Motorola, Inc.
英文描述: 10 AMP SUBMINIATURE POWER RELAY
中文描述: 通信處理器模塊
文件頁數: 39/74頁
文件大小: 234K
代理商: MPC823UM_REV1_16-CPM7
Communication Processor Module
MOTOROLA
MPC823 REFERENCE MANUAL
16-417
S
C
1
P
16.11.7.11 SMCx TRANSPARENT TRANSMIT BUFFER DESCRIPTOR.
Data is sent to
the communication processor module for transmission on an SMCx channel by arranging it
in buffers referenced by the channel’s transmit (TX) buffer descriptor table. Using the buffer
descriptors, the communication processor module confirms transmission or indicates error
conditions so that the processor knows the buffers have been serviced.
R—Ready
0 = The data buffer associated with this buffer descriptor is not ready for transmission
and you are free to manipulate it or its associated data buffer. The communication
processor module clears this bit after the buffer is transmitted or after an error
condition is encountered.
1 = The data buffer, which you prepare for transmission, is not transmitted yet or is
currently being transmitted. You cannot write any fields of this buffer descriptor
once this bit is set.
Bits 1, 5, 7–13, and 15—Reserved
These bits are reserved and must be set to 0.
W—Wrap (Final Buffer Descriptor in Table)
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is
used, the communication processor module receives incoming data into the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table is programmable and determined by the W bit and overall
space constraints of the dual-port RAM.
I—Interrupt
0 = No interrupt is generated after this buffer is serviced.
1 = The TX and TXE bits in the SMCE–Transparent register are set when this buffer is
serviced. TX and TXE can cause interrupts if they are enabled.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OFFSET + 0
R
RES
W
I
L
RES
CM
RESERVED
UN
RES
OFFSET + 2
DATA LENGTH
OFFSET + 4
TX DATA BUFFER POINTER
OFFSET + 6
NOTE:
You are only responsible for initializing the items in bold.
Note:
The communication processor module sets all the status bits in this buffer
descriptor, but you must clear them before submitting the buffer descriptor to the
communication processor module.
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