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參數資料
| 型號： | TFP6424PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁數： | 2/65頁 |
| 文件大小： | 813K |
| 代理商： | TFP6424PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VID
Differential input sensitivity
150
1560
mVp-p
t(1)
Analog input intra-pair (+ to -) differential skew time
0.4
tbit
t(2)
Analog Input inter-pair or channel-to-channel skew time
1
tpix§
t(3)
Worse case differential input clock jitter tolerance
TBD
ns
tr(1)
Rise time of data and control signals#, ||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
2.9
3.1
ns
tf(1)
Fall time of data and control signals#, ||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
2.84
3.2
ns
tr(2)
Rise time of ODCK clock#
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
tf(2)
Fall time of ODCK clock#
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
tsu(1)
Setup time, data and control signal to falling edge of ODCK
(OCK_INV = low)||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
th(1)
Hold time, data and control signal to falling edge of ODCK
(OCK_INV = low)||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
tsu(2)
Setup time, data and control signal to rising edge of ODCK
(OCK_INV = high)||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
th(2)
Hold time, data and control signal to rising edge of ODCK
(OCK_INV = high)||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
f(ODCK)
ODCK frequency
PIX = Low (1-PIX/CLK)
25
112
MHz
f(ODCK)
ODCK frequency
PIX = High (2-PIX/CLK)
12.5
56
MHz
ODCK duty-cycle
40%
50%
60%
td(1)
Propagation delay time from PD low to Hi-Z outputs
9
ns
td(2)
Propagation delay time from PDO low to Hi-Z outputs
9
ns
td(3)
Delay time from PD rising edge to inputs active
ns
td(4)
Pulse duration, minimum time PD low
ns
tt(1)
Transition time between DE transition to SCDT lowk
1e6
tpix
tt(2)
Transition time between DE transition to SCDT highk
1280
tpix
ts(1)
Delay time, ODCK latching edge to QE[23:0] data output
STAG = Low,
Pixs = High
0.25
tpix
Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.
tbit is 1/10 the pixel time, tpix
§ tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in
2-pixel/clock mode.
Measured differentially at 50% crossing using ODCK output clock as trigger.
# Rise and fall times measured as time between 20% and 80% of signal amplitude.
|| Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1]
kLink active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
PRODUCT
PREVIEW
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