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參數(shù)資料
| 型號(hào)： | TFP6424PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 3/65頁(yè) |
| 文件大小： | 813K |
| 代理商： | TFP6424PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description
overview
TFP6422 and TFP6424 integrates multiple video output interfaces in a single device in a compact 64-pin TQFP
package. It supports all the most commonly used PC and consumer video standards as follows:
D DVI
D Composite video
–
NTSC–M
–
PAL–B,D,G,H,I
–
PAL–M
–
PAL–N
–
PAL–Nc
D S–Video
D SCART interface
D YPrPb Component video
D Analog RGB output
TFP6422 and TFP6424 integrates video encoder, color space converter, horizontal and vertical scaler,
flicker-reduction filter, two PLLs, four DACs, DVI encoder, and three differential pairs of T.M.D.S. drivers. A
dedicated high-speed low-pin count video pixel port transfers high-bandwidth digital video data from a graphics
controller or other digital video source to the TFP6422 and TFP6424. All video modes share the same video
pixel port.
The TFP6422 and TFP6424 is versatile and highly programmable to provide maximum flexibility for the users.
An I2C host interface is provided to program and configure the TFP6422 and TFP6424.
The TFP6424 also conforms to the Macrovision 7.11 copy protection scheme.
default modes after reset
Depending on the state of the INT0/CBARE pin, TFP6422 and TFP6424 is reset to one of two default modes.
If INT0/CBARE is pullup, TFP6422 and TFP6424 will be initialized to be in DVI transmitter mode. If INT0/CBARE
pin is pull-down, TFP6422 and TFP6424 will be initialized to be in simultaneous composite and S-video out
mode, and will display an internally generated color bar.
I2C interface
The I2C interface is used to access the internal TFP6422 and TFP6424 registers. This two–pin interface
consists of one clock line, SCL, and one serial data line, SDA. The basic I2C access cycles are shown in
Figures 1 and 2.
SDA
Start Condition (S)
Stop Condition (P)
SCL
Figure 1. I2C Stop and Stop Conditions
PRODUCT
PREVIEW
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