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參數資料
| 型號： | TFP6424PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁數： | 40/65頁 |
| 文件大小： | 813K |
| 代理商： | TFP6424PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PLL_BWRNG
Subaddress = 4E
Default = 0x00
7
6
5
4
3
2
1
0
PLL_BW[1:0]
PLL_ADJ
PLL_SEL
PLL_HI[1:0]
PLL_LO[1:0]
PLL_BW[1:0]
PLL filter bandwidth control. PLL_BW[1:0] selects the bandwidth of the PLL loop filter when
TFP6422/6424 is in DVI output mode (VIDOUT[2:0] = 000). The default value is 00 after reset. Users
should always use the default value except when the signal conditions on the reference clock
(CLKIN0 and CLKIN1) are too noisy. The narrower bandwidth results in better noise and jitter
immunity of the reference clock at the expense of longer lock time.
00(*)
Normal bandwidth
01
Wide bandwidth
10
Narrow bandwidth
11
Reserved
In nonDVI output modes, PLL_BW[1:0] is ignored and the loop filter bandwidth is fixed internally and
cannot be changed.
PLL_ADJ
PLL range adjustment select
0(*)
PLL range adjustment is automatic
1
PLL range is manually adjusted by programming PLL_SEL, PLL_LO[1:0] and
PLL_HI[1:0]
PLL_SEL
PLL select
0(*)
Low–range PLL is selected
1
High–range PLL is selected
PLL_HI[1:0]
High–range PLL range select
00(*)
Highest Frequency
01
10
11
Lowest frequency
PLL_LO[1:0]
Low–range PLL range select
00(*)
Highest frequency
01
10
11
Lowest frequency
PRODUCT
PREVIEW
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