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參數資料
| 型號： | TFP6424PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁數： | 34/65頁 |
| 文件大小： | 813K |
| 代理商： | TFP6424PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
digital video out (DVO) interface diagram
Graphic
TFP6422/6424
DVO I/F
Intel-Based
DVI
TV-Out
Terminal Functions
TERMINAL
NAME
POWER
RAIL
NO.
I/O
DESCRIPTION
Digital Video Input Port
INT0/CBARE
DVDD
9
I/O
Interrupt for hot plug support (Output)
INT0 is an open drain signal and an assertion low interrupt request informing the graphics
controller of Flat Panel/TV/secondary monitor hot–plug or hot unplug event. For normal
applications, a 10K pull-up resistor must be connected between this pin and DVCC.
Color bar display enable at reset (Input)
For diagnostics purpose, this pin can be pulled down via a pulldown resistor to enable the video
encoder to output the color bar test signal upon the completion of reset. The state of this pin
is sensed immediately after the low-to-high transition of RST. If the state of this pin is LOW,
the video encoder will be enabled and output the color bar test signal. If the state of this pin
is HIGH, DVI transmitter will be enabled and analog video will be disabled.
CLKIN[1:0]
DVDD
57, 56
I
TFP6422/6424 uses CLKIN [1:0] to clock in video data and timing control signals. When used
as a differential pair, CLKIN0 connects to the positive end and CLKIN1 connects to the
negative end. For single–ended clock input, the clock is connected to CLKIN0 and a reference
voltage of VDDQ/2 must be connected to CLKIN1.
During TV mode, CLKIN [1:0] must be connected to CLKOUT or a clock signal derived from
the graphics controller.
During LCD mode, the graphics controller should use internal DOT clock to generate
CLKIN[1:0].
PRODUCT
PREVIEW
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