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參數(shù)資料
| 型號： | THS8083APZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 13/63頁 |
| 文件大小： | 320K |
| 代理商： | THS8083APZPG4 |
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37
Phase-
Frequency
Detector
HS
Programmable
Divider
MUX
I
N
V
POL
PROG.
LOOP
FILTER
PFD_FREEZE
LOCK
12
to ADC
MUX
ADCCLK1
(see NOTE)
ADCCLK2
DTOCLK3
DTO
EXT_ADCCLK
Phase
Selector
INV2
1
HS_POL
TERM_CNT
PHASESEL
SEL_ADCCLK
DIV3
1
INV3
1
D
I
V
2
DIV2
1
PLLCLK
GAIN_N
3
33
GAIN_P
NOM_INC
SELCLK
DTO_DIS
I
N
V
D
I
V
2
1
Noise
Gate
1
HS_MS
HS_WIDTH
3 P
5
1
DISABLE_
DIV
3
Lock
Detection
Hysteresis
LD_THRESH
8
VCOCLK
(From Analog PLL)
NOTE: ADCCLK1 is used by the output formatter to generate the DATACLK1 output.
1
DHS_MODE
8
Compensated in Output
Formatter for Pipeline
Data Delay. Then Output
on Terminal DHS With
Polarity Determined by
<DHS_POL>.
PFD
Figure 36. Digital PLL
The device provides three clock outputs. One output signal, DATACLK1, is derived from the ADC clock output. It is
actually equal to the sampling clock, but compensated in phase so that its rising edge always corresponds to the
center valid region of the output data. Output data timing (setup/hold) is specified with respect to this rising edge.
Therefore, DATACLK1 is typically used for clocking the THS8083A’s output data. The frequency of DATACLK1 is
either equal to, or one half the sampling clock, depending on the operation mode of the output formatter. When the
THS8083A is clocked with an external sampling clock, this external clock is used as the source to generate
DATACLK1 in the output formatter.
The second clock output, ADCCLK2, is equal to the ADC sampling clock, but can optionally be divided by 2 and
inverted.
The third clock output, DTOCLK3, is always derived from the PLL output clock, irrespective of the use of an external
sampling clock on EXT_ADCCLK. So, when operating with an external sampling clock, the DTOCLK3 output can be
used to generate a second, possibly asynchronous, clock signal in either open or closed loop operation locked to a
reference HS input. Also, DTOCLK3 can be optionally divided by 2 and inverted.
The divide and invert functions are implemented to enable a two-part master/slave operation in case sampling speeds
higher than 80 MSPS are required. In this case, the master uses its PLL to generate a line-locked clock, and its inverse
is used by the second slave device as an external sampling clock.
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