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參數(shù)資料
| 型號： | THS8083APZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 36/63頁 |
| 文件大小： | 320K |
| 代理商： | THS8083APZPG4 |
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52
5.2
Timing Diagram—16-Bit Parallel Mode
This is the ITUR.BT601 style mode typically used in YUV operation of the part with a Y analog input connected
to the Ch1 input of the THS8083A, and with Cb and Cr connected to the Ch2 and Ch3 inputs, respectively. The
DATACLK1 output is at the sampling clock frequency and Ch3 remains unused. The output bus B of all channels is
high impedance. The HS_D signal can be used to uniquely identify output data Cb from Cr.
DATACLK
CH1_OUTA[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH1_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
DHS
02
HS
Cb: From Ch.2 Input
Cr: From Ch.3 Input
pix 01
pix 02
ADCCLK2
03
tPLH(OE)
tPHL(OE)
tsu(OUT)
th(OUT)
01
th(DHS)
tsu(DHS)
<DHS_MODE> = 1 > Width
Equal to Width of HS Input
<DHS_MODE> = 0 > DHS
Width is 1 ADCCLK2 Period
7 ADCCLK2
Cycles Latency
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
7 ADCCLK2 Cycles Latency
Last Samples From Previous Line
01(Cr)
01(Cb)
03(Cb)
Last Samples From Previous Line
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