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參數資料
| 型號： | THS8083APZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 29/63頁 |
| 文件大小： | 320K |
| 代理商： | THS8083APZPG4 |
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322
3.11.46 Register Name: CH2_RDBK
Subaddress: 33 (R)
CH2_RDBK7
MSB
LSB
CH2_RDBK6
CH2_RDBK5
CH2_RDBK4
CH2_RDBK3
CH2_RDBK2
CH2_RDBK1
CH2_RDBK0
CH2_RDBK[7..0]:
Readback register of ADC channel 2
Default: (changed during operation)
3.11.47 Register Name: CH3_RDBK
Subaddress: 34 (R)
CH3_RDBK7
MSB
LSB
CH3_RDBK6
CH3_RDBK5
CH3_RDBK4
CH3_RDBK3
CH3_RDBK2
CH3_RDBK1
CH3_RDBK0
CH3_RDBK[7..0]:
Readback register of ADC channel 3
Default: (changed during operation)
3.11.48 Register Name: OFM_CTRL
Subaddress: 40 (R/W)
X
MSB
LSB
X
DHS_MODE
DHS_POL
OFM_MODE1
OFM_MODE0
DHS_MODE
Controls how DHS (display horizontal sync output) is generated. DHS can be a version of the signal on the
HS input terminal, synchronized to the sampling clock and compensated for the data pipeline delay through
the part (see timing diagrams). This preserves the HS width but has the disadvantage that, for some phase
settings, there is a one-pixel uncertainty on the exact timing of DHS (if HS falls within setup/hold time of the
input register that is clocked by the ADC sampling clock).
Therefore, a second option exist to generate DHS as the output pulse of the PLL feedback divider. Since this
pulse is generated once for every <TERM_CNT> cycles of the DTO clock, the uncertainty is resolved. This
can avoid possible horizontal line jitter on the display system. The width of the DHS pulse is in this case
always 1 ADC clock cycle, independent of the width of the incoming HS. This method also assures the
generation of a DHS pulse on every line, even when no incoming HS is present or when it is filtered out by
sync processing (e.g., from composite sync extraction).
0 = DHS is generated from the output of the PLL feedback divider (default)
1 = DHS is generated as a latched and delayed version of HS input
DHS_POL
Controls polarity of the DHS output
0 = positive polarity (default)
1 = negative polarity
OFM_MODE[1..0]:
Defines mode of output formatter and frequency on DATACLK1 as in Table 32.
Table 31. Output Formatter
OFM_MODE
[1..0]
DESCRIPTION
DATACLK1 OUT-
PUT FREQUENCY
00 (default)
24-bit parallel mode:
24-bit output on bus A, bus B is Hi-Z
Fs
01
16-bit mode
16-bit output on ch1 and ch2 of bus A, with data from ch2 and ch3 downsampled by 2 (parallel 4:2:2
CCIR601 mode), bus B is Hi-Z
Fs
10
48-bit interleaved mode
48-bit output on buses A and B at half sampling rate. Data on bus B shifted by 1 Fs clock.
Fs/2
11
48-bit parallel mode
48-bit output on buses A and B at half sampling rate
Fs/2
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