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參數(shù)資料
| 型號(hào)： | THS8083APZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁(yè)數(shù)： | 38/63頁(yè) |
| 文件大小： | 320K |
| 代理商： | THS8083APZPG4 |
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54
5.4
Timing Diagram—48-Bit Parallel Mode
This mode allows a double-pixel width output interface with no time offset between buses A and B. The DATACLK1
output is at half of the sampling clock frequency. Data on output bus A precedes data on output bus B.
Last Samples From Previous Line
DATACLK
CH1_OUTA[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH1_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
01
05
DHS
tdlh(OE)
tdhl(OE)
tsu(DHS)
th(DHS)
tsu(OUT)
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
<DHS_MODE> = 1 > Width
Equal to Width of HS Input
<DHS_MODE> = 0 > DHS
Width is 1 ADCCLK2 Period
7 ADCCLK2
Cycles Latency
pix 01
pix 02
ADCCLK1
Last Samples From Previous Line
03
th(OUT)
04
02
01
05
Last Samples From Previous Line
03
Last Samples From Previous Line
04
02
01
05
Last Samples From Previous Line
03
Last Samples From Previous Line
04
02
7 ADCCLK2 Cycles Latency
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