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參數(shù)資料
| 型號： | THS8083APZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 44/63頁 |
| 文件大小： | 320K |
| 代理商： | THS8083APZPG4 |
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6.4.8
Output Formatter/Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclk
Maximum conversion rate
THS8083A
80
MHz
fclk
Minimum conversion rate
13
MHz
tsu(OUT)
Setup time
1.6
ns
th(OUT),
th(DHS)
Hold time
With respect to 50% level of rising
edge on DATACLK
1
ns
tsu(DHS)
Setup time
edge on DATACLK
2
ns
tPLH(OE)
Propagation (delay) time, low-to-high
See Note 13
9.5
ns
tPHL(OE)
Propagation (delay) time, high-to-low-level output
See Note 13
8.5
ns
DATACLK1 output duty cycle
40%
60%
HS and data pipeline delay
See Note 14
See timing diagrams
NOTES: 13. Output timing—OE timing tPLH(OE) is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The
digital output load is not higher than 10 pF.
OE timing tPHL(OE) is measured from the VIL(MAX) level of OE to the instant when the output data reaches VOH(min) or VOL(max)
output levels. The digital output load is not higher than 10 pF.
14. Pipeline delay (latency)—The number of clock cycles between conversion initiation on an input sample and the corresponding
output data being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.
6.4.9
PLL
6.4.9.1 Open Loop
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DTO frequency range, f(DTO)
THS8083A
See Note 15
13
80
MHz
Instantaneous jitter, t(INS)
260
ps
Short-term jitter, t(JOS)
See Note 15
800 (pp)
240 (rms)
1250 (pp)
485 (rms)
ps
Phase Increment
See Note 15
11.25
Monotonic
deg
NOTE 15: PLL characterization:
Instantaneous jitter is the pk-pk position variation of the clock rising edge between succeeding periods.
Short term jitter in open loop or closed loop is defined as the variation of the clock rising edge within one PLL update period (within
the same video line). This can be visually measured by capturing the clock and displaying it on a digital scope with a persistency of
one video line. Numerically, the time instants of the rising edges, at a defined voltage level, of a number N of clock cycles (N = 800)
are captured at a high sampling rate. The average clock time period is calculated from these time instants. The deviation between
each actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value
along one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.
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