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參數資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數： | 16/71頁 |
| 文件大小： | 267K |
| 代理商： | TSB12LV01APZ |
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2–2
2.1.3
The receiver takes incoming data from the PHY interface and determines if the incoming data is addressed
to this node. If the incoming packet is addressed to this node, the CRC of the packet header is checked.
If the header CRC is good, the header is stored in the GRF. For block and isochronous packets, the
remainder of the packet is stored one quadlet at a time. The receiver places a status quadlet in the GRF
after the last quadlet of the packet is checked in the GRF. The status quadlet contains the error code for the
packet. The error code is the acknowledge code that was or could have been sent for that packet. For
broadcast packets that do not need an acknowledge packet, the error code is the acknowledge code that
would have been sent. This acknowledge code tells the transaction layer whether or not the data CRC is
good or bad. When the header CRC is bad, the header is flushed and the rest of the packet is ignored. Bad
packets are automatically flushed by the receiver.
Receiver
When a cycle-start message is received, it is detected and the cycle-start message data is sent to the cycle
timer. The cycle-start messages can be placed in the GRF like other quadlet packets.
2.1.4
The TSB12LV01A contains two transmit FIFOs (ATF and ITF) and one receive FIFO (GRF). Each of these
FIFOs is one quadlet wide and their length is software selectable. These software-selectable FIFOs allow
customization of the size of each FIFO for individual applications. The sum of all FIFOs cannot be larger
than 512 quadlets. The transmit FIFOs are write only from the host bus interface, and the receive FIFO is
read only from the host bus interface. FIFO sizes must not be changed on the fly. All transactions must be
ignored and FIFOs cleared before changing the FIFO sizes.
Transmit and Receive FIFOs
An example of how to use software-adjustable FIFOs follows:
In applications where isochronous packets are large and asynchronous packets are small, the
implementers can set the ITF to a large size, 200 quadlets, and set the ATF to a smaller size, 100
quadlets.This means 212 quadlets are allocated to the GRF. Notice that the sum of all FIFOs is equal to 512
quadlets. Only the ATF size and the ITF size can be programmed, the remaining space is assigned to the
GRF.
2.1.5
The cycle timer is used by nodes that support isochronous data transfer. The cycle timer is a 32-bit
cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as
defined in the IEEE 1394-1995 standard. In the TSB12LV01A, the cycle-timer register is implemented in the
cycle timer and is located in IEEE-1212 initial register space at location 200h. It can also be accessed
through the host bus at address 14h. The cycle timer contains the cycle-timer register. The cycle-timer
register consists of three fields; cycle offset, cycle-count, and seconds count. The low-order 12 bits of the
timer are a modulo 3072 counter, which increments once every 24.576-MHz clock periods (or 40.69 ns).
The next 13 higher-order bits are a count of 8,000-Hz (or 125
μ
s) cycles, and the highest 7 bits count
seconds. The timer can be disabled using the cycle-timer-enable bit in the control register.
Cycle Timer
The cycle timer has two possible sources. The first cycle-source option is when the cycle source (CySrc)
bit in the configuration register is set, then the CYCLEIN input causes the cycle-count field to increment for
each positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros. CYCLEIN
should only be the source when the node is cycle master. When the cycle-count field increments,
CYCLEOUT is generated.
The second cycle-source option is when the CySrc bit is cleared. In this state, the cycle-offset field of the
cycle-timer register is incremented by the internal 24.576-MHz clock. The cycle timer is updated by the
reception of the cycle-start packet for the noncycle master nodes. Each time the cycle-offset field rolls over,
the cycle-count field is incremented and the CYCLEOUT signal is generated. The cycle-offset field in the
cycle-start packet is used by the cycle-master node to keep all nodes in phase and running with a nominal
isochronous cycle of 125
μ
s.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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