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參數資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數： | 61/71頁 |
| 文件大小： | 267K |
| 代理商： | TSB12LV01APZ |
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7–1
7 TSB12LV01A to 1394 Phy Interface Specification
7.1
Introduction
This chapter provides an overview of a TSB12LV01A to the phy interface. The information that follows can
be used as a guide through the process of connecting the TSB12LV01A to a 1394 physical-layer device.
The part numbers referenced, the TSB41LV03 and the TSB12LV01A, represent the Texas Instruments
implementation of the phy (TSB41LV03) and link (TSB12LV01A) layers of the IEEE 1394-1995 standard.
The specific details of how the TSB41LV03 device operates are not discussed in this document. Only those
parts that relate to the TSB12LV01A phy-link interface are mentioned.
7.2
The TSB12LV01A is capable of supporting 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s phy-layer devices. For
that reason, this document describes an interface to a 400-Mbits/s (actually 393.216-Mbits/s) device. To
support lower-speed phy layers, adjust the width of the data bus by two terminals per 100 Mbits/s. For
example, for 100-Mbits/s, 200-Mbits/s, and 400-Mbits/s devices, the data bus is 2, 4, and 8 bits wide
respectively. The width of the CTL bus and the clock rate between the devices, however, does not change
regardless of the transmission speed that is used.
Assumptions
Finally, the 1394 phy layer has control of all bidirectional terminals that run between the phy layer and
TSB12LV01A. The TSB12LV01A can drive these terminals only after it has been given permission by the
phy layer. A dedicated request terminal (LREQ) is used by the TSB12LV01A for any activity that the link
wishes to initiate.
7.3
The functional block diagram of the TSB12LV01A to phy layer is shown in Figure 7–1.
Block Diagram
ISO
ISO
D0 – D7
CTL0 – CTL1
LREQ
SCLK
1394
Link
Layer
1394
Phy-Layer
Device
TSB12LV01A
NOTE A: See Table 2–2 for signal definition.
Figure 7–1. Functional Block Diagram of the TSB12LV01A to Phy Layer
7.4
The four operations that can occur in the phy-link interface are request, status, transmit, and receive. With
the exception of the request operation, all actions are initiated by the phy layer.
Operational Overview
The CTL0 – CTL1 bus is encoded as shown in the following sections.
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| TSB3055 | IC APEX 20KE FPGA 300K 240-PQFP |
| TSB41AB3 | IC APEX 20KE FPGA 400K 672-FBGA |
| TSB41BA3-EP | IC APEX 20KE FPGA 400K 672-FBGA |
| TSB41LV03PFP | IC APEX 20KE FPGA 600K 652-BGA |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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